Electrical computers and digital data processing systems: input/ – Interrupt processing – Source or destination identifier
Reexamination Certificate
2006-01-05
2009-06-02
Rinehart, Mark (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Source or destination identifier
C709S216000, C714S005110, C714S006130, C714S006130, C714S006130
Reexamination Certificate
active
07543096
ABSTRACT:
A fault-tolerant mass storage system includes two RAID controllers that communicate via a PCI-Express link. Each controller has a bus bridge coupled to the link, a cache memory that caches user data for storage on disk drives controlled by the controllers, and a CPU. The CPU fetches and executes program instructions from a CPU memory coupled to it. The CPU programs the bus bridge with window information defining a window of locations within the CPU memory, which is less than an entirety of the CPU memory. The bus bridge receives data on the link from the other controller and if the header of a packet containing the data indicates it is destined for the CPU memory, the bus bridge translates the address of the data so as to write the data safely to the CPU memory, but only within the window and nowhere else within the CPU memory.
REFERENCES:
patent: 4217486 (1980-08-01), Tawfik et al.
patent: 4251869 (1981-02-01), Shaffer
patent: 4428044 (1984-01-01), Liron
patent: 5345565 (1994-09-01), Jibbe et al.
patent: 5408644 (1995-04-01), Schneider et al.
patent: 5483528 (1996-01-01), Christensen
patent: 5530842 (1996-06-01), Abraham et al.
patent: 5553023 (1996-09-01), Lau et al.
patent: 5613068 (1997-03-01), Gregg et al.
patent: 5619642 (1997-04-01), Nielson et al.
patent: 5619644 (1997-04-01), Crockett et al.
patent: 5668956 (1997-09-01), Okazawa et al.
patent: 5680579 (1997-10-01), Young et al.
patent: 5706283 (1998-01-01), Suzuki
patent: 5754884 (1998-05-01), Swanstrom
patent: 5802602 (1998-09-01), Rahman et al.
patent: 5812754 (1998-09-01), Lui et al.
patent: 5881254 (1999-03-01), Corrigan et al.
patent: 6009275 (1999-12-01), DeKoning et al.
patent: 6038680 (2000-03-01), Olarig
patent: 6058455 (2000-05-01), Islam et al.
patent: 6094699 (2000-07-01), Surugucchi et al.
patent: 6098140 (2000-08-01), Pecone et al.
patent: 6185652 (2001-02-01), Shek et al.
patent: 6223252 (2001-04-01), Bandera et al.
patent: 6243829 (2001-06-01), Chan
patent: 6272533 (2001-08-01), Browne
patent: 6397293 (2002-05-01), Shrader et al.
patent: 6421769 (2002-07-01), Teitenberg et al.
patent: 6438603 (2002-08-01), Ogus
patent: 6470429 (2002-10-01), Jones et al.
patent: 6493795 (2002-12-01), Arsenault et al.
patent: 6502157 (2002-12-01), Batchelor et al.
patent: 6507581 (2003-01-01), Sgammato
patent: 6629179 (2003-09-01), Bashford
patent: 6718408 (2004-04-01), Esterberg et al.
patent: 6732243 (2004-05-01), Busser et al.
patent: 6839788 (2005-01-01), Pecone
patent: 6912621 (2005-06-01), Harris
patent: 6944617 (2005-09-01), Harriman
patent: 7046668 (2006-05-01), Pettey et al.
patent: 7069368 (2006-06-01), Thornton
patent: 7071946 (2006-07-01), Jeddeloh
patent: 7107343 (2006-09-01), Rinaldis et al.
patent: 7149819 (2006-12-01), Pettey
patent: 7457902 (2008-11-01), Yang et al.
patent: 2001/0013076 (2001-08-01), Yamamoto
patent: 2002/0029319 (2002-03-01), Robbins et al.
patent: 2002/0069317 (2002-06-01), Chow et al.
patent: 2002/0069334 (2002-06-01), Hsia et al.
patent: 2002/0083111 (2002-06-01), Row et al.
patent: 2002/0091828 (2002-07-01), Kitamura et al.
patent: 2002/0099881 (2002-07-01), Gugel
patent: 2002/0194412 (2002-12-01), Bottom
patent: 2003/0065733 (2003-04-01), Pecone
patent: 2003/0065836 (2003-04-01), Pecone
patent: 2003/0217211 (2003-11-01), Rust et al.
patent: 2004/0064638 (2004-04-01), Chong, Jr.
patent: 2004/0177126 (2004-09-01), Maine
patent: 2004/0221198 (2004-11-01), Vecoven
patent: 2005/0044169 (2005-02-01), Arbeitman et al.
patent: 2005/0102549 (2005-05-01), Davies et al.
patent: 2005/0102557 (2005-05-01), Davies et al.
patent: 2006/0106982 (2006-05-01), Ashmore et al.
patent: 2006/0161707 (2006-07-01), Davies et al.
patent: 2006/0230218 (2006-10-01), Warren et al.
patent: 2006/0242312 (2006-10-01), Crespi et al.
patent: 2006/0248308 (2006-11-01), Wang et al.
patent: 2006/0248400 (2006-11-01), Miyamoto
patent: 2006/0277347 (2006-12-01), Ashmore et al.
patent: 2006/0282701 (2006-12-01), Davies et al.
patent: 2008/0005410 (2008-01-01), Mies et al.
patent: 2008/0005470 (2008-01-01), Davies
patent: 2008/0201616 (2008-08-01), Ashmore
patent: 0800138 (1997-10-01), None
patent: 0817054 (1998-01-01), None
patent: 0967552 (1999-12-01), None
patent: 2396726 (2004-06-01), None
patent: 2001142648 (2001-05-01), None
patent: WO0182077 (2001-11-01), None
patent: WO2006124217 (2006-11-01), None
patent: WO2007002219 (2007-01-01), None
PCI-SIG. PCI Express Base Specification Revision 1.0a. Apr. 15, 2003.
Makijarvi, Petri. PICMG1.3 SHB Raid Performance. Evaluating next generation high-performance PC 4U computers. Jul. 4, 2007.
Luse, Paul. The Benefits of RAID on Motherboard. May 2003.
Overland Storage. Tiered Data Protection Made Simple. 2008.
Budruk et al. “PCI Express System Architecture.” Addison Wesley Professional. Sep. 4, 2003.
“DCM PCI-X Verification Services” Datasheet #1. DCM Technologies, 39675 Cedar Blvd., #220, Newark, CA 94560.
“PCI-X Synthesizable Core.” inSilicon Corporation. San Jose, CA. 1999.
“IBM 133 PCI-X Bridge” Datasheet. Apr. 6, 2001.
“IBM 133 PCI-X Bridge” Datasheet 2000. IBM Microelectronics Division.
“Tsi320™ Software Initialization Application Note.” Oct. 2001. 80A600B—AN002—01. Tundra Semiconductor Corporation.
“PCI-X Bus Test Environment.” 1999. inSilicon Corporation 411 East Plumeria Dr. San Jose, CA 95134.
“1005 IDT Precise PCI-Express Family Presentation.” Integrated Device Technology.
“COMPAQ Rapid Enabler for PCI-X (CREX) Initiator Interface.” (Preliminary). Revision 0.28 Sep. 2, 1999.
“COMPAQ Rapid Enabler for PCI-X (CREX) Target Bus Interface.” (Preliminary). Revision 0.36 Sep. 2, 1999.
“Intel 41210 Serial to Parallel PCI Bridge Product Brief.” Intel Corporation. 2003.
Pericom. “Bridge Products Road Map.” Customer Presentation. pp. 31, 33-35.
IDT. “24-lane 3-Port PCI Express Switch” Product Brief. 89PES24N3. Dec. 22, 2005. Integrated Device Technology, Inc.
“PEX 8104” Data Book. Version 0.61. Mar. 2004. PLX Technology, Inc.
“PEX 8114 PCI Express to PCI/PCI-X Bridge.” Product Brief. Version 2.0. 2004. PLX Technology, Inc.
“Tsi320™ PCI/X-to-PCI/X Bus Bridge Manual.” Jan. 2001. 80A600B—MA001—02. Tundra Semiconductor Corporation.
“Tsi320™ Dual-Mode PCI-to-PCI Bus Bridge Errata.” Sep. 2001. 80A600B—ER001—05. Tundra Semiconductor Corporation.
“Tsi320™ Dual-Mode PCI-to-PCI Bus Bridge User Manual.” Jun. 2001. 80A600B—MA001—04. Tundra Semiconductor Corporation.
“Corex-V10 PCI-X Initiator/Target” Datasheet #1. DCM Technologies, 39675 Cedar Blvd., #220, Newark, CA 94560.
“X-caliber Design Specification: PCI-2.2/PCI-X Megacell” Rev 0.99.3. Nov. 19, 1999.
Young et al.A high I/O reconfigurable crossbar switch. 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003. Apr. 9-11, 2003. pp. 3-10.
Landman et al.Activity-sensitive architectural power analysis. IEEE Transactions in Computer-Aided Design of Integrated Circuits and Systems. Jun. 1966. pp. 571-587.
U.S. Office Action for U.S. Appl. No. 09/967,027, filed Apr. 30, 2004, pp. 1-7 and cover sheet.
U.S. Office Action for U.S. Appl. No. 09/967,126, filed Mar. 7, 2005, pp. 1-5 and cover sheet.
European Examination Report for Application No. GB0406742.7, dated Nov. 10, 2004.
European Examination Report for Application No. GB0406739.3, dated Nov. 10, 2004.
European Examination Report for Application No. GB0406740.1, dated Nov. 10, 2004.
DCM Presentation. DCM Technologies, 39675 Cedar Blvd. #220, Newark, CA 94560.
“PEX 8114: PCI-X-PCI Express Bridge.” Data Book. Version 0.70. May 2004. PLX Technology, Inc.
“Corex-V10 PCI-X Initiator/Target” Datasheet #2. DCM Technologies, 39675 Cedar Blvd., #220, Newark, CA 94560.
“DCM Corex-V10 FAQ.” version 1.00. DCM Technologies, 39675 Cedar Blvd., #220, Newark, CA 94560.
ID
Davis E. Alan
Dot Hill Systems Corporation
Huffman James W.
Rinehart Mark
Spittle Matthew D
LandOfFree
Safe message transfers on PCI-Express link from RAID... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Safe message transfers on PCI-Express link from RAID..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Safe message transfers on PCI-Express link from RAID... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4081172