Safe logic zero and one supply for CMOS integrated circuits

Details Safe logic zero and one supply for CMOS integrated circuits Safe logic zero and one supply for CMOS integrated circuits

1988-04-15

1989-09-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 307443, 307448, 307451, 307491, 361 58, 361 91, 361111, H03K 301, H03K 1716, H03K 19094

Patent

active

048689033

ABSTRACT:
A circuit for supplying safe logic zero and logic one signals to hardwired inputs of CMOS ICs comprises, at most, three field effect transistors, none of which have gates connected to either drain voltage V.sub.dd or source voltage V.sub.ss. The circuit has no external inputs and has two outputs, logic zero and logic one. The circuit has only one stable operating point and moves to this operating point from any initial condition. The circuit is safe and can enhance the reliability of ICs as it provides the same noise protection from voltages V.sub.ss and V.sub.dd for nodes connected to its output that an inverter provides for nodes connected to its output.

REFERENCES:
patent: 3638039 (1972-01-01), Chen et al.
patent: 4595941 (1986-06-01), Avery
patent: 4616172 (1986-10-01), Rahim
"CMOS Supply Sequence Circuit", IBM Technical Disclosure Bulletin, vol. 29, No. 1, Jun. 1986, pp. 221-222.
"Transient Protection With Parasitic SCRs", Electronic Product Design, vol. 6, No. 4, Apr. 1985, pp. 93-95.

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