Sacrificial self-aligned interconnect structures

Details Sacrificial self-aligned interconnect structures Sacrificial self-aligned interconnect structures

2008-09-05

2010-11-02

Cao, Phat X (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S304000, C257SE27086

Reexamination Certificate

active

07825450

ABSTRACT:
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed.

REFERENCES:
patent: 4786954 (1988-11-01), Morie et al.
patent: 4855952 (1989-08-01), Kiyosumi
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5120677 (1992-06-01), Wakamatsu
patent: 5166084 (1992-11-01), Pfiester
patent: 5286344 (1994-02-01), Blalock et al.
patent: 5343354 (1994-08-01), Lee et al.
patent: 5389559 (1995-02-01), Hsieh et al.
patent: 5395786 (1995-03-01), Hsu et al.
patent: 5429978 (1995-07-01), Lu et al.
patent: 5594682 (1997-01-01), Lu et al.
patent: 5763931 (1998-06-01), Sugiyama
patent: 5795804 (1998-08-01), Jenq
patent: 5811283 (1998-09-01), Sun
patent: 5827765 (1998-10-01), Stengl et al.
patent: 5981330 (1999-11-01), Jenq
patent: 6168986 (2001-01-01), Walker et al.
patent: 6995072 (2006-02-01), Walker et al.
patent: 7427793 (2008-09-01), Walker et al.
patent: 2006/0113576 (2006-06-01), Walker et al.
Nesbit et al., A 0.6 μm2 256Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), IEDM 93-627 through 630, pp. 26.2.1 through 26.2.4, 0-7803-1450-6, © 1993 IEEE.

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