Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Physical deformation
Reexamination Certificate
2008-04-15
2008-04-15
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Physical deformation
Reexamination Certificate
active
07358580
ABSTRACT:
A method comprising over an area of a substrate, forming a plurality of three dimensional first structures; following forming the first structures, conformally introducing a sacrificial material over the area of the substrate; introducing a second structural material over the sacrificial material; and removing the sacrificial material. An apparatus comprising a first structure on a substrate; and a second structure on the substrate and separated from the first structure by an unfilled gap defined by the thickness of a removed film.
REFERENCES:
patent: 4918032 (1990-04-01), Jain et al.
patent: 5399415 (1995-03-01), Chen et al.
patent: 5963788 (1999-10-01), Barron et al.
patent: 6012336 (2000-01-01), Eaton et al.
patent: 6082197 (2000-07-01), Mizuno et al.
patent: 6127812 (2000-10-01), Ghezzo et al.
patent: 6210988 (2001-04-01), Howe et al.
patent: 6229684 (2001-05-01), Cowen et al.
patent: 6230566 (2001-05-01), Lee et al.
patent: 6297072 (2001-10-01), Tilmans et al.
patent: 6329738 (2001-12-01), Hung et al.
patent: 6495387 (2002-12-01), French
patent: 6617657 (2003-09-01), Yao et al.
patent: 6739190 (2004-05-01), Hsu et al.
patent: 19852878 (2000-05-01), None
patent: 0928959 (1999-07-01), None
patent: 0947816 (1999-10-01), None
PCT International Search Report dated Feb. 10, 2003, Intel Corporation, International Application No. PCT/US02/20764.
Clark T.-C. Nguyen, “Micromachining technologies for miniaturized communication devices,” SPIE vol. 3511, Santa Clara, CA, Sep. 1998, pp. 24-38.
Yang, Zhenchuan, et al., “GaN on Patterned Silicon (GPS) Technique for Fabrication of GaN-Based Mems,” IEEE, 2005, pp. 887-890.
Fujimori, T., et al., “Fully CMOS Compatible ON-LSI Capacitive Pressure Sensor Fabricated Using Standard Back-End-Of-Line Processes,” IEEE, 2005, pp. 37-40.
Takeuchi, Hideki, et al., “Ge-Blade Damascene Process for Post-CMOS Integration of Nano-Mechanical Resonators,” IEEE, vol. 25, No. 8, Aug. 2004, pp. 529-531.
Hsu, Wan-Thai, et al., “A Sub-Micron Capacitive Gap Process for Multiple-Metal-Electrode Lateral Micromechanical Resonators,” IEEE, 2001, pp. 349-352.
Cheng Peng
Ma Qing
Blakely , Sokoloff, Taylor & Zafman LLP
Coleman W. David
Intel Corporation
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