Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1995-08-30
1997-05-20
Kunemund, Robert
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
216 38, 438723, H01L 21465
Patent
active
056311974
ABSTRACT:
A method for forming a sacrificial planarization layer over an SOG layer which provide a more planar final surface. A substrate is provided with a first insulating layer formed on its surface. A spin-on-glass (SOG) layer is formed over the first insulating layer. The SOG layer has a greater thickness towards the outer edge compared to the central area of the substrate. Next a sacrificial layer is formed over the SOG layer. The sacrificial layer, preferably formed of silicon oxide material, is formed so that the layer has a greater thickness towards the outside of the wafer than in the central area. Next, the sacrificial layer is etched away and portions of the SOG layer are etched. The etch rates of the sacrificial layer, the SOG layer and the first insulating layer are approximately equal so that the planar top SOG surface is transferred to the final top surface after the etch. The resulting surface is planar because the additional sacrificial layer thickness in the outside periphery compensated for the thinner SOG in on the periphery and the faster etch rate on the periphery.
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Chen Lung
Huang Yuan-Chang
Jang Syun-Ming
Yu Chen-Hua
Alanko Anita
Kunemund Robert
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company Ltd
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