Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-08-29
2004-09-28
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S370000, C438S510000, C438S531000, C438S914000, C438S923000
Reexamination Certificate
active
06797596
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor manufacture and, more particularly, to a sacrificial layer used as a screening material during implantation of doping material into active areas of a semiconductor wafer.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor devices such as memory devices, logic devices, and microprocessors, various process steps are commonly performed. For instance, a semiconductor wafer is commonly oxidized to form a layer of silicon dioxide for various uses such as gate oxide which eventually separates memory array access transistor stacks from the wafer. The wafer is also commonly doped or implanted to increase or decrease its intrinsic electrical conductivity.
FIGS. 1 and 2
depict conventional process steps used during the formation of a semiconductor device.
FIG. 1
depicts an unetched transistor gate stack assembly comprising the following structural elements: a semiconductor wafer
10
, for example comprising monocrystalline silicon; a gate oxide layer
12
comprising silicon dioxide formed by oxidizing silicon wafer
10
; a blanket layer of polycrystalline silicon (polysilicon)
14
; a metal layer, for example tungsten silicide
16
, which enhances conductivity of polysilicon layer
14
; a dielectric capping layer
18
; and a patterned photoresist layer
20
. After forming the
FIG. 1
structure, an etch is performed using the resist as a pattern to result in the structure of
FIG. 2
, which depicts first and second transistor gate stacks
22
. The etch includes etching through the dielectric capping layer
18
, the metal layer
16
, the polysilicon layer
14
, and only partially through gate oxide
12
. A portion of oxide
12
remains in the exposed areas between the transistor gate stacks
22
, either formed as a result of native oxidation of the silicon wafer if the silicon is exposed during the etch or remaining from an under etch of the gate oxide. This oxide
12
protects the silicon regions not protected from the implant depicted in
FIG. 2
by the transistor gate stacks. The implant of
FIG. 2
forms doped transistor source and drain regions
24
.
The arrangement of silicon atoms within the single crystal structure of the semiconductor wafer forms crystalline lattice channels, or uniform spaces, between adjacent silicon atoms. These channels within the silicon crystal structure provide a path along which implanted ions may travel without encountering silicon atoms to slow their progress. Channeling occurs when dopants enter these channels during implantation, and result in ions traveling either too far into the semiconductor wafer or into undesired locations within the wafer. Channeling makes it difficult to control the electrical properties of the wafer and may lead to device leakage to the substrate or between structures or other adjacent implanted regions, shorting of adjacent structures, or other reduced electrical properties. Instances of channeling are known to decrease with increasing energy, because the ion's direction of travel is less likely to be altered with increased implantation energy. Additionally, channeling decreases with increasing doping concentration (dose), because the crystal structure of the wafer is altered and the channels become less uniform with higher bombardment of ions. Also, channeling decreases with increasing ion size.
One method used to reduce channeling of implanted dopants includes tilting the wafer relative to the direction of the implant. Tilting reduces channeling by implanting ions into the wafer in a number of different directions (off-axis) relative to the direction of the channel in the crystal lattice, and thus the dopants have less likelihood of entering the crystal channels. Tilting the wafer during implantation, however, may result in dopants entering the channel region under the transistor gate stacks. Tilting also requires implanting the wafer in many different directions to ensure complete implantation symmetry for gate stacks of different orientations and to avoid shadowing.
Another method of reducing channeling is to further oxidize the wafer surface subsequent to etching the transistor gate stacks to form a thicker oxide layer between the transistor stacks. Forming this oxide reduces channeling by providing a layer which randomizes the direction of travel of the ions, thereby allowing fewer ions to enter the crystal channels. A drawback to this method is that the oxide forms over the sidewalls of the transistor gate stack by oxidizing the polysilicon gate layer
16
. This layer may be subsequently removed using an isotropic etch; however oxidizing the polysilicon gate effectively narrows or “shortens” the transistor gate and increases resistance of the word line, making the implant less self-aligned to the transistor gate edge. Forming a conformal deposited layer over the sidewalls and then implanting the diffusion regions would result in a gap (under-lap) in the implanted region between the edge of the transistor gate and the edge of the diffusion region, thereby resulting in an electrical disconnect between the transistor gate and the diffusion region.
A method and structure for decreasing channeling in semiconductor wafers would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method which, among other advantages, reduces problems associated with the manufacture of semiconductor devices, particularly channeling which may occur during ion implantation. In accordance with one embodiment of the invention, a wafer substrate assembly is formed to include a plurality of transistor gate stacks. Subsequently, a screening layer is formed over horizontal surfaces of the wafer assembly, for example over the top of the transistor gate stack capping layers and over horizontal regions between the transistor gate stacks. The screening layer comprises a material having straight-line deposition properties such as a layer of amorphous carbon, or more than one such layer.
After forming the screening layer an implant is performed through the screening layer. As the ions travel through the screening layer they collide with atoms in the screening layer, and thus the direction of ion travel is randomized. This significantly reduces ion channeling by reducing the number of ions which enter channels of the silicon crystal lattice structure of the wafer.
After implanting the wafer through the screening layer, the screening layer is removed, for example using an anisotropic plasma etch. In another embodiment, the screening layer may remain in place during various other processing steps if it has positive effects such as a masking function, or at least if it has no net negative effects. In this instance, a photoresist layer may be formed overlying the screening layer, and may be used to pattern the screening layer for one or more additional etch steps. If the screening layer is not immediately removed after implanting the wafer, it is eventually removed. After removal of the screening layer wafer processing continues according to means known in the art.
Advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
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Endo, Kazuhiko et al., “Effect of Bias Addition on the Gap Filling Properties of Fluorinated Armorphous Carbon Thin Films Grown by Helicon Wave Plasma-Enhanced Chemical Vapor Deposition”, Jpn. J. Appl. Phys.(35), pp. L1348-L1350, Oct. 15, 1996.
Ahmed Fawad
Mathew Suraj J
Trivedi Jigish D.
Martin Kevin D.
Micro)n Technology, Inc.
Rocchegiani Renzo
Smith Matthew
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