Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-19
2001-07-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S645000, C438S672000, C438S699000, C438S701000, C438S759000, C438S760000
Reexamination Certificate
active
06258711
ABSTRACT:
FIELD OF INVENTION
This invention relates to the fabrication of semiconductors. More particularly, it relates to a process in which a sacrificial layer is added and used in conjunction with chemical-mechanical polishing to substantially reduce “dishing” and “erosion” of metallic or other inlaid patterns formed by damascene, dual damascene, or like processes.
BACKGROUND OF INVENTION
The fabrication of very large scale integrated circuits on silicon wafers is a process requiring extreme precision because of the very fine details of the circuits. Indeed, the width of circuit lines are continually decreasing, as the technology advances, and are now in the 0.18-100 micron range. Since these circuits are produced using photolithographic techniques, extremely accurately ground lenses are required to provide such fine detail. As a necessary consequence of providing such precise focusing, the lenses lack depth of field, i.e. an image is accurately produced only at a specific distance from the lens, and any deviation in this distance produces an increasingly unfocused or fuzzy image. Therefore, the surface onto which the image is projected must be as perfectly planar as possible to eliminate out of focus image fuzziness. A failure to maintain planarity exacerbates the problem as additional layers are formed on the nonplanar surface resulting in an increased proportion of defective semiconductors that must be rejected.
A standard technique for restoring surface planarity after inlaying metal in dual-damascene structures within a dielectric layer, is chemical-mechanical planarization (CMP). During this process, the surface of the wafer is polished, with a polishing pad and a chemical slurry, to remove excess metal and to replanarize it. The slurries contain an abrasive such as silica or alumina, and chemical additives that are designed to selectively react with and soften the composition of those components that must be planarized on the wafer surface. Accordingly, polishing slurries may be selected to enhance the removal rate of a particular component on the surface of the wafer, taking into account that certain of the components may be inherently more easily removed purely by abrasive action.
While aluminum has been the preferred conductive metal used in semiconductor circuitry in the past, the more recent trend is towards copper, which is a superior electrical conductor, using damascene and dual damascene (also known as “inlaid metallization”) process techniques. This trend towards using damascene and dual-damascene inlaying of metal lines and vias has presented new challenges in semiconductor fabrication. It has been found that during CMP there are often unacceptable levels of “dishing” and “erosion” of copper surfaces. Indeed, depressions of about 1,000 Å or more may be formed. As pointed out above, as near perfect a planar surface is needed to enable modern fine line circuits. Dishing and erosion therefore present serious issues in the damascene and dual damascene metal inlay technology. The issues are illustrated schematically in
FIGS. 1A
, B and C. In
FIG. 1A
, a patterned substrate
2
, for example an oxide layer, forms the underlying pattern structure to be filled with a fill composition, usually a metallic conductor, to form lines or vias. The patterned structure
2
includes a series of down features
4
and up features
6
. The recesses
8
formed between the up and down features are filled with a fill material. As shown in
FIG. 1A
, a conformal intermediate layer (such as a “barrier”, “liner” or “adhesive” layer)
12
is formed over the patterned layer or substrate
2
. A conformal fill layer
14
is formed over the barrier layer
12
.
In the prior art, chemical-mechanical polishing is applied to the structure shown in
FIG. 1A
, to produce the structure shown in
FIG. 1B
, wherein the major portion of the fill material
14
has been removed. The fill material is homogeneous and sufficiently thick that planarization is usually achieved before pattern clearing commences. Once pattern clearing commences, the dishing and erosion issues arise. Thus, upon further polishing for pattern clearing, removal of the thin layer of fill material
14
that extends above the up features
6
of the conformal layer, produces the structure shown in FIG.
1
C. Because the CMP is designed to have the highest polish or removal rate for the fill material, and a lower rate on the intermediate layer (or substrate, in the absence of such a layer), the inlaid material continues to be removed at a higher rate. This results in “dishing” of the inlaid material
14
, in that the upper surfaces of the material are not coplanar with the up features of patterned structure
2
. Instead, the upper surfaces of fill material
14
in the recesses are “dished” below the surfaces of up feature
6
. Moreover, pattern clearing uniformity across the wafer is not perfect, so that overpolish is necessary to clear the pattern on all semiconductors being fabricated in the wafer. Overpolish further aggravates the dishing problem that results from unmatched material selectivity, as explained above.
Dishing is often accompanied by erosion, a different but related topographical feature. Erosion arises when recesses of the fill material cause stress concentrations at fine matrix/substrate features which increase polish rates locally and result in pattern deterioration.
The lack of planarity that is caused by dishing and erosion is undesirable for several reasons, including the resultant undesirable large variations in pattern features (size and density), as well as for those reasons discussed above. Thus, dishing and erosion and should be reduced as far as possible, or eliminated if feasible.
SUMMARY OF THE INVENTION
The invention provides a method of reducing dishing and erosion of inlaid material surfaces thereby improving the planarity of the surface of a semiconductor wafer and reducing the reject rate of semiconductors caused by the dishing and erosion problem. The invention is particularly applicable to those semiconductor fabrication processes using the damascene or dual damascene processes.
In accordance with an embodiment of the invention, an optional conformal intermediate layer is formed over patterned surface structure on the semiconductor wafer. This surface structure typically includes “up” (raised) features and “down” (recessed) features. Lines and vias are formed in the recesses of the down features. In damascene-type processes, a conformal fill layer, usually metallic, is formed over the intermediate layer, or directly over the patterned substrate, if such layer is not present. This fill layer has a thickness sufficient such that its down features are vertically spaced from up features of the underlying intermediate layer. The degree of vertical spacing between the down features of the fill layer and the up features of the intermediate layer or patterned substrate constitute an amount of “overfill”. A sacrificial conformal layer (or preferential deposition of a sacrificial composition on the down features) is formed over the fill layer. This sacrificial layer or fill is preferably designed to be removed in pattern clearing at about the same time or slightly before the intermediate layer, using chemical-mechanical polishing (CMP). This can be achieved in several ways, for example, it may be of about the same thickness (or slightly thicker) and of the same or similar material as the intermediate layer.
Upon initial polishing of the wafer surface, up features of the sacrificial layer are removed along with underlying fill (which is removed at a faster rate), until residual down features of the sacrificial layer are exposed to the polisher. The surface then includes these residual down features as “caps” on the fill in the patterned substrate. Upon further polishing for pattern clearing, the caps of the sacrificial layer are removed along with up features of the intermediate layer. This produces a surface wherein the upper surfaces of the patterned fills (or “inlaid material”) have reduced dishing and er
Berry Renee R.
Merchant & Gould
Nelms David
SpeedFam-IPEC Corporation
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