Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-09
2002-11-26
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06487709
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to configuration of programmable logic devices, and more particularly to run-time configuration of routing resources.
BACKGROUND
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
The field of reconfigurable computing has advanced steadily for the past decade, using FPGAs as the basis for high-performance reconfigurable systems. Run-Time Reconfigurable (RTR) systems distinguish themselves by performing circuit logic and routing customization at run-time. RTR systems using FPGAs are expected to result in systems that require less hardware, less software, and fewer input/output resources than traditional FPGA-based systems. However, scarcity of software that supports RTR is believed to be one reason that RTR has been outpaced by research in other areas of reconfigurable computing.
Whereas with traditional configuration of FPGAs the time taken to generate a programming bitstream is generally not real-time critical, with RTR systems, the time required to generate the programming bitstream may be critical from the viewpoint of a user who is waiting for the FPGA to be reconfigured. Thus, it may be acceptable to take hours to generate a programming bitstream using traditional configuration methods. In a runtime environment, however, it is expected that the reconfiguration process require no more than a few seconds or even a fraction of a second.
Reconfiguration of a FPGA may include routing and rerouting connections between the logic sections. Routers in a traditional configuration process generally route connections for all the circuit elements. That is, these routers define connections for all the circuit elements in a design, expending a great deal of time in the process. In an RTR environment, traditional routing methods are inappropriate given the real-time operating constraints. Present run-time routing methods provide a great deal of program control over the routing process. For example, the JBits program from Xilinx allows a program to manipulate individual bits in the configuration bitstream for configuring routing resources. While this approach provides a great deal of flexibility, the drawback is added program complexity.
A system and method that addresses the aforementioned problems, as well as other related problems, is therefore desirable.
SUMMARY OF THE INVENTION
A system and method for configuring routing resources of a programmable logic device are presented in various embodiments. In one embodiment, a first application programming interface is provided which automatically generates configuration bits for configuration of routing resources to connect a source to a sink. The input parameters to the to the first interface include the source and the sink. A second programming interface is provided to automatically generate configuration bits for configuration of routing resources that connect a source to a plurality of sinks. The second interface is responsive to input parameters specifying the source and plurality of sinks. Additional program interfaces are provided to allow greater control over the routing process.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.
REFERENCES:
patent: 5737580 (1998-04-01), Hathaway et al.
patent: 5946478 (1999-08-01), Lawman
patent: 6078736 (2000-06-01), Guccione
patent: 6112020 (2000-08-01), Wright
patent: 6216259 (2001-04-01), Guccione et al.
patent: 6311316 (2001-10-01), Huggins et al.
Guccione Steven A.
Keller Eric R.
Levi Delon
Maunu LeRoy D.
Niebling John F.
Whitmore Stacy A
Xilinx , Inc.
Young Edel M.
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