Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
1999-05-25
2001-05-15
Duda, Kathleen (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S313000, C216S017000, C438S691000
Reexamination Certificate
active
06232043
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of chemical mechanical planarization with particular reference to planarizing shallow trenches that have been over filled with HDP oxide.
BACKGROUND OF THE INVENTION
With the growing need for higher densities in integrated circuits, the STI (shallow trench isolation) process has gradually replaced the LOCOS (local oxidation of silicon) process. The STI process begins with the formation of shallow trenches in the surface of the silicon wafer following which these trenches are over-filled with a suitable dielectric material, typically silicon oxide, the excess being then removed by means of CMP (chemical mechanical polishing). In principle, the advancing etch front during CMP should be flat and independent of the initial surface contours, hence its popularity for planarization. In practice, however, the advancing front is not always as flat as would be desired, being influenced as much by the nature of the materials being etched as by the initial surface contour. For example, the CMP removal rate of an oxide layer will be lower where it is underlaid by another layer of oxide and higher where it is underlaid by a layer of metal.
As a consequence, the amount of material that is removed after CMP, as well as the time needed to remove it, will vary from one wafer to the next if the underlying metal patterns (which in turn depend on the particular technology and circuits that are being implemented) are different.
Clearly, it is possible to determine the optimum polishing time for any given class of wafers by purely empirical means such as conducting a test run involving several different polishing times each time a new wafer design is to be implemented. Pilot runs of this type are, however, very time-consuming (typically 8-10 hours), rendering this approach expensive, particularly if the technology being calibrated is not to be manufactured in large quantities.
There have, therefore, been a number of suggested approaches as to how to determine the optimum polishing time (i.e. the optimum amount of dielectric to be removed) without the need to go through a pilot run.
For example, Li et al. (U.S. Pat. No. 5,659,492) measure the times to first break through the film being polished. Then the time to completely remove the film is measured and the two numbers are added to give the total required polishing time.
Cote (U.S. Pat. No. 5,234,868) determines an end point for CMP by using an underlayer of different visual appearance from the layer that is being removed.
Schoenborn et al. (U.S. Pat. No. 5,298,110) first measure removal rates inside and outside the trenches to determine their relative polishing rates. This information is used to predict optimum polishing times for future wafers.
Sahota et al. (U.S. Pat. No. 5,665,199) first polish at least two test wafers then measure the amount removed in four selected locations so as to characterize the extent of polish rate variation across the wafer. They then use this data to determine the optimum polishing time.
Hoffman et al. (U.S. Pat. No. 5,552,996) divide the wafer surface up into a number of sub-regions. Optimum polishing time is determined for each sub-region and this data is then used to compute an optimum polishing time for a full wafer.
All of these approaches, while possibly representing an improvement over a full blown pilot study, are still very time-consuming. The present invention presents an approach that involves two hours or less to implement but that nevertheless provides a highly reliable guide as to how much material is to be removed in any particular case.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a method for achieving shallow trench isolation in minimal time with little or no dishing at the surfaces of the trenches.
Another object of the invention has been to provide a simple formula whereby the required amount of HDP oxide needed to achieve planarization can be readily computed from several easily determined quantities.
These objects have been achieved by noting that there is a linear relationship between the amount of material that needs to be removed in order to achieve full, but dishing free, planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions above the active areas that are etched out of the dielectric prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.
REFERENCES:
patent: 5234868 (1993-08-01), Cote
patent: 5298110 (1994-03-01), Schoenbron et al.
patent: 5552996 (1996-09-01), Hoffman et al.
patent: 5659492 (1997-08-01), Li et al.
patent: 5665199 (1997-09-01), Sahota et al.
patent: 5763310 (2000-07-01), Gardner
patent: 5834359 (1998-10-01), Jeng et al.
patent: 5851899 (1998-12-01), Wiegand
patent: 5882983 (1999-03-01), Gardner et al.
patent: 5904539 (1999-05-01), Hause et al.
patent: 5981354 (1999-11-01), Spikes et al.
patent: 5981357 (1999-11-01), Hause et al.
patent: 6080620 (2000-06-01), Jeng
patent: 6087705 (2000-07-01), Gardner et al.
Chang Wen-Pin
Lin Hway-Chi
Lin Yu-Ku
Wang Ying-Lang
Ackerman Stephen B.
Duda Kathleen
Saile George O.
Taiwan Semiconductor Manufacturing Company
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