Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-15
2002-01-22
Smith, Matthew S (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06341366
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the editing of physical integrated circuit layouts, more particularly to a rule-driven method and system for editing physical integrated circuit layouts.
2. Description of the Related Art
With the reduction in hardware cost and substantial advances in very large scale integrated circuit (VLSI) technology, integrated circuit products have become available for widespread use. In the meantime, the soaring complexity of VLSI design follows continuous progress in the fabrication process, which still tracks the claim of Moore's Law that the memory size should double every eighteen months.
An overview of a typical full-custom integrated circuit design process is shown in FIG.
1
. As illustrated, the design process can be divided into front-end and back-end design phases. The front-end design phase includes circuit design and circuit simulation. The back-end design phase includes layout design, layout verification and layout simulation. As the integrated circuit industry moves towards deep sub-micron technology and the wiring delays keep on increasing, the relationship between the two design phases grows much closer, and the entire design cycle may be lengthened due to more iterations in the two design phases.
The present invention puts focus on the reduction of the back-end design phase cycle. As shown in
FIG. 1
, the back-end design phase cycle depends mainly on layout design and layout verification. Design rule checking (DRC) is an important step in layout verification, which verifies the constraints, if existing, in one layer or between any two layers, in a physical integrated circuit layout. Traditionally, layout engineers have no idea about the distance between two working shapes of the circuit layout unless manual measurement is performed, which will interrupt layout editing. While layout editor tools provide layout engineers with manual measurement to achieve a desired distance between two working shapes whose spacing is constrained by the design rules, manual measurement as such is often inaccurate and time-consuming. Some negligence, such as incorrect distance due to inaccurate manual measurement and the use of incorrect design rules, may be left unnoticed until entering the layout verification stage, thereby resulting in the need to perform one or more design iterations. The duration of the design iteration process may range from hours to days. Moreover, fabrication technology is upgraded year by year, and layout engineers need to comply with the design rules, which are dependent upon the fabrication technology, during the layout design cycle. There is thus a problem in that layout engineers need to get familiar with design rules corresponding to a new fabrication technology within a short period of time. Also, it is easy for layout engineers to confuse the design rules of the new fabrication technology with those of older ones. Practice and training often cost much time that further prolong the design cycle.
In summary, conventional layout tools require layout engineers to manually measure the distance of two edges, between which there exists a spacing constraint. Manual measurement bothers layout engineers and may result in poor accuracy. Also, having no idea about whether the circuit layout violates some design rules during layout editing will likely lead to failure during the verification stage. Therefore, accurate and convenient distance measurement that takes into account the design rules of the applied fabrication technology without retentive faculty is thus needed to reduce much of the overload of layout engineers and shorten the back-end design phase cycle.
Patents related to circuit layouts include U.S. Pat. Nos. 5,604,680, 5,625,564 and 5,768,479. In U.S. Pat. No. 5,604,680, there is disclosed a method and system for the symbolic design of an integrated circuit layout using only topological features of cells in the layout, absent geometrical information. In U.S. Pat. No. 5,625,564, there is disclosed a method and system for extracting devices from a hierarchical cell design. In U.S. Pat. No. 5,768,479, there is disclosed an automatic physical layout placement technique whereby, according to a specified template, corresponding positions among circuit elements in the template or certain specified layout patterns can be preserved as much as possible when the original design is implemented using new fabrication technology or when minor modifications are made to the original design. In this patent, fuzzy logic is employed to evaluate the positioning cost of circuit elements for both the new physical layout and the specified template and to determine the located positions that meet maximum similarity. The processing unit is a circuit element that has meaningful functionality for electronic behavior. This patent is concerned with the relative positioning of the circuit elements. The object of this patent is to keep the positioning similarity among the circuit elements of the physical layout and the schematic layout in order to enable the layout designer to accurately control circuit parameters, such as cross talk and parasitic components. Positioning preservation is a necessity for certain parasitic-sensitive circuits, such as analog circuits and some application specific circuits.
Unlike the aforesaid patents, the present invention focuses on real-time detection of design rule violations, and can adjust the geometry of working shapes such that no unintentional design rule violations occur when layout designers edit the physical integrated circuit layout. The units processed in the present invention are the edges or corners of multi-edged working shapes. This is in contrast with a circuit element, which consists of working shapes in different layers. The present invention is not only concerned with the issue of providing layout designers with a real-time quick reference to design rule violation status among the selected boundaries of target working shapes and the boundaries of neighboring working shapes, but is also concerned with the issue of aiding designers during the editing stage by automatically rebounding the selected boundaries of target working shapes to appropriate positions such that no design rule violations occur.
SUMMARY OF THE INVENTION
Therefore, the main object of the present invention is to provide a rule-driven method and system for editing physical integrated circuit layouts, wherein major design rule violations are detected and are resolved in advance of the verification stage so that the number of design iterations (i.e. editing and verification) can be reduced in order to shorten the entire design cycle.
Another object of the present invention is to provide a rule-driven layout editing method and system that utilizes a fabrication technology file which can be upgraded in order to allow layout engineers to adapt quickly when applying new fabrication technology.
According to one aspect of the present invention, a rule-driven method for editing a physical integrated circuit layout comprised of a plurality of multi-edged working shapes, comprises the machine executed steps of:
creating a desired one of the working shapes that is shown on a computer monitor;
calculating a width value associated with the desired one of the working shapes;
verifying if the width value violates a minimum distance as defined by relevant design rules of an applied fabrication technology, including the steps of extracting the relevant design rules from a fabrication technology file, and comparing the width value with the relevant design rules; and
automatically adjusting geometry of the desired one of the working shapes to comply with the relevant design rules upon verification that the width value violates the minimum distance.
According to another aspect of the present invention, a rule-driven system for the automated editing of a physical integrated circuit layout that is comprised of a plurality of multi-edged working shapes, comprises:
a monitor for showing the physical integrated cir
Li Yih-Lang
Wang Jui-Chien
Merchant & Gould P.C.
Smith Matthew S
Spring Soft Inc.
Thompson A. M.
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