RTL back annotator

Details RTL back annotator RTL back annotator

2001-06-12

2002-08-27

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06442738

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to systems and methods for providing ASIC (Application Specific Integrated Circuit) simulation, and more particularly to an RTL back annotator for applying back annotations in RTL (Register Transfer Language), thereby providing fast ASIC simulations utilizing back annotated data.
BACKGROUND OF THE INVENTION
Electronic system design for single or multiple chip circuits is becoming extremely complex. Because of the size of circuits being designed, breadboard prototyping is typically no longer feasible. Thus, some type of simulation of the circuit being designed is necessary. Presently, at-speed gate level simulations are utilized for verifying actual timing performance for an ASIC array after layout. A back-annotation file provides the actual metal delays for the ASIC layout combined with the actual fan-out and wire-OR delays for internal nets, actual package pin, and system capacitive load delays.
Due to ever increasing complexity, gate level simulation often cannot be easily computed. In particular, gate level simulations utilizing back annotated data often take long periods of time to run. Consequently, formal verification using a timing verifier is often used to verify verifying actual timing performance of an ASIC array. Timing verifiers attempt to predict circuit performance under real-time conditions without actually running simulations using back annotated data. However, such verifiers typically require that the designer develop a different model, increasing the effort required. Further, in some instances, it may still be necessary or desirable to provide actual simulation in addition to formal verification.
RTL simulations typically run much faster than comparable gate level analyses, often providing upwards of a ten fold decrease in run time. However, RTL simulations presently do not allow for consideration of back annotated data for verifying actual timing performance for an ASIC array after layout, as do gate level simulations or formal verification. Consequently, there exists a need to provide a means of applying back annotated data to the RTL code of an RTL simulation for verifying actual timing performance for an ASIC array after layout during RTL simulation.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an RTL back annotator for applying back annotated data to the RTL code of an RTL simulation for verifying actual timing performance for an ASIC array after layout during RTL simulation. In exemplary embodiments, the RTL back annotator parses through annotation data from the back annotation file for the ASIC layout. RTL delays are then generated for delays in the ASIC layout. These RTL delays are then applied to the RTL compiled design, thereby emulating the delays that a gate level netlist would have. In this manner, an RTL simulation having timings of the real layout may be run.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.


REFERENCES:
patent: 5910897 (1999-06-01), Danelo et al.
patent: 5933356 (1999-08-01), Rostoker et al.
patent: 5991523 (1999-11-01), Williams et al.

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