RTL annotation tool for layout induced netlist changes

Details RTL annotation tool for layout induced netlist changes RTL annotation tool for layout induced netlist changes

2001-04-30

2003-03-04

Tokar, Michael (Department: 2819)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06530073

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally computer-aided design (CAD) tools such as Electronic Design Automation (EDA) tools, hardware description languages, and logic synthesis for electronic circuit design.
2. Description of Related Art
Modern digital design of complex circuits and systems, which can contain millions of interconnected gates, involves a number of techniques for manageable design. Tools using CAD, EDA, hardware description languages (HDL), logic synthesis, hierarchy design, and “divide and conquer” strategies such as top-down design are employed.
A hardware description language (HDL) representation of a circuit is a representation of a circuit in text rather than graphically, enabling a more uniform, portable representation of the circuit, one that can be manipulated by a computer program. Currently, Verilog and VHDL are two major standards of HDLs. HDL may be stylized into “structural” (e.g. at the gate-level), “behavioral” or “dataflow” (typically at the higher level description of a circuit), or any combination of the above. HDL representations are used in logic synthesis, the conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the “netlist”.
An HDL description of a system can be written at an intermediate level language referred to as a Register Transfer Level (RTL). A subset of RTL that is used by logic synthesis tools (such as Synopsys' DesignCompiler and Cadence's Ambit) is known as “synthesizable RTL”. A logic synthesis tool with a library of components can convert a RTL description into an interconnection of primitive components that implements the circuit, subject to any specified constraints, such as timing, speed, power consumption and area constraints. Typically, these constraints are specified by the designer of the circuit. The output of the logic synthesis tool, after an optimization process referred to as technology mapping, is a so-called netlist of interconnected storage elements, gates, and other functional blocks (note the term “net” is also a keyword in Verilog, and represents a data type comprising a physical connection between structural elements). The netlist output serves as input to physical design tools that physically place the logic elements and route the interconnections between them to produce a manufacturing circuit layout. When programmable parts are employed, such as field-programmable gate arrays, binary information is produced by design tools to program the logic within the parts.
Hierarchy design involves following an inverted tree in design, with the top-level design of the circuit at the root and more increasingly specific levels of detail at the branches and leaves below. Functional blocks (or modules, with the term “module” also a keyword in Verilog HDL) are employed at the upper echelons of the tree, while primitive blocks (such as NAND gates) are employed at the lower echelons. In theory the design process is “top down”, where the circuit function is specified by text, with constraints on cost, performance and reliability, and then the circuit is designed by repeatedly dividing it into blocks as necessary. In practice, in order to obtain reusability and to make maximum use of predefined modules, it is often necessary to perform portions of the design bottom up. In addition, bottom up design is sometimes necessary to eliminate violations of constraints in a preliminary specification. When a preliminary original design of a circuit has to modified or changed it is termed an engineering change order (ECO), and the subsequently modified or changed original design of the circuit may be termed a modified circuit, post-layout annotated circuit, post-layout circuit, or ECO circuit.
The term ECO (Engineering Change Order) is commonly used to represent a variety of concepts. An ECO may refer to a functional change, in which the functionality of the circuit has changed and is no longer logically equivalent to the pre-ECO (original) design. An ECO may also refer to a non-functional change, in which the new design remains functionally equivalent to the original design. Typically non-functional type of changes are made in order to change the timing behavior of the circuit, or to accommodate manufacturability issues encountered during layout (e.g., overloaded cells that result in signal ramp times that are outside the characterized range of operation of the cell). Non-functional changes in an ECO may be introduced by the designer, the layout engineer, or by CAD tools during physical implementation (layout).
There are several categories of non-functional ECO changes in a circuit: physical-only transformations and gate-level transformations. Physical-only non-functional ECO changes are not reflected in the gate-level netlist. Examples of non-functional physical-only ECO changes are changing the placement of a cell, re-implementing the routing of a signal
et, or modifying the physical location of physical pins. A gate-level non-functional ECO transformation is a type of change that may change the gate level netlist by the introduction of new cells, swapping of cells for different drive strength logically-equivalent cells, or local logic restructuring (i.e., re-synthesis of a specific logic cone to create an alternative gate-level representation).
ECO changes submitted after a significant amount of physical implementation has occurred are very problematic, given today's commercial Electronic Design Automation (EDA) tool offering. Since the physical realization (placement, routing and physical optimization) of a design for large circuits may involve months of engineering effort and many resources (both software and hardware), preserving as much of the prior physical implementation as possible is of paramount importance when incorporating logic changes into a design once physical implementation has begun. While today's physical design tools offer some capabilities for dealing with ECOs, they are not capable of preserving netlist changes that have been introduced during layout. Specifically, today's physical design tools allow comparison of the netlist representation inside of the tool's database with an external gate-level netlist. As a result of this comparison, the physical design tool identifies changes that must be made to the database (i.e., deletion/addition of cells and deletion/addition of connections between the cells) to make the database consistent with the external netlist. For ECOs that are implemented manually at the gate-level by the designer (as opposed to modifying the source RTL and creating a new gate-level netlist through logic synthesis), this mechanism works fine as long as the modifications are made to the post-layout netlist from the previous iteration of the layout.
However, this approach to introducing ECOs to a design has several significant drawbacks:
(1) The source description of the design is generally considered the HDL/RTL, not the gate-level netlist. Maintaining an accurate representation of the design in RTL is critical to ensure that future generations of a design can leverage the current design description (i.e., migration from one technology to another, specialization/generalization of a design, integration of the design into a larger design). Functional modifications made at the gate-level cannot be easily propagated to the new generations of a design.
(2) If the ECO is manually implemented in the gate-level netlist, the gate-level netlist is no longer guaranteed to be functionally equivalent to the source RTL (since it was not technically feasible to manually implement an equivalent change at the RTL level, this technically feasible to manually implement an equivalent change at the RTL level, this is often extremely difficult to do, and generally requires use of formal verification tools to ensure that the changes are truly equivalent.
(3) For large-scale functional changes to functional blocks/modules, it may be impractical to manually make the changes

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