RRAM backend flow

Details RRAM backend flow RRAM backend flow

2006-04-11

2006-04-11

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07028274

ABSTRACT:
A method for transforming a customer's memory design into an RRAM memory design. A port mapping table is created that lists the ports of the customer memories, and an instance types table is created that lists the customer memories. For each customer memory that is listed in the instance types table, any virtual buffer nets are removed, and any virtual buffers are removed. Any loose nets so created are reconnected to an RRAM cell in the RRAM memory design. The customer memory instance are then removed. A constraints file is updated from customer memory port designations to RRAM port designations. Automated test logic is inserted into the RRAM memory design, layout on the RRAM memory design is performed, and timing constraints on the RRAM memory design are satisfied. A modified version of the RRAM memory design is returned to the customer for verification. The modified version is made using the port mapping table. Each RRAM matrix is replaced with the customer memories it replaced, the removed virtual buffer nets and virtual buffers are left out, and other parts of the RRAM memory design are left unchanged.

REFERENCES:
patent: 5825662 (1998-10-01), Trimberger
patent: 5838954 (1998-11-01), Trimberger
patent: 6732343 (2004-05-01), Frerichs et al.
patent: 2005/0125751 (2005-06-01), Miller et al.
patent: 2005/0183054 (2005-08-01), Wein et al.

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