Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-18
2002-10-22
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000, C438S683000, C438S704000, C438S706000, C438S717000, C438S738000, C438S745000, C438S756000
Reexamination Certificate
active
06468904
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the resist protective oxide (RPO) layer to improve salicide processes in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, silicidation processes are often used in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
It may be desired to perform silicidation on one part of a wafer while protecting another portion of the wafer from silicidation. A resist protective oxide (RPO) layer is deposited over semiconductor device structures and then selectively removed where silicidation is desired. The RPO layer will prevent silicidation where it remains over the semiconductor device structures.
Wet or dry etch processes can be used to selectively remove the RPO layer. In the wet etch process, typically dipping in dilute hydrofluoric acid (DHF), long DHF dipping time will cause the recessing of the underlying gate electrode spacer liner layer and also shallow trench isolation (STI) oxide loss. Spacer recessing can cause active area shorting and yield loss due to metal residue being inserted under the spacer. STI loss is one of the major concerns causing a “double hump” in the I-V curve and leakage. In the dry etch process, high substrate loss and active area damage are observed. These will cause shallow junction damage or poor salicide, formation. It is desired to find a new film scheme and etch process to improve the RPO process window.
U.S. Pat. No. 5,998,252 to Huang, U.S. Pat. No. 6,015,730 to Wang et al, U.S. Pat. No. 5,863,820 to Huang, and U.S. Pat. No. 6,004,843 to Huang discuss salicide processes using a conventional RPO layer. U.S. Pat. No. 6,046,103 to Thei et al discloses a salicide process. RPO is not disclosed.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for improving junction leakage performance in a salicide process in the fabrication of integrated circuits.
It is a further object of the invention to provide a process for forming an improved RPO layer in a salicide process in the fabrication of integrated circuits.
Yet another object is to form a composite RPO film and a two-step etching process to improve junction leakage performance in a salicide process.
A still further object of the invention to provide a process for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits.
In accordance with the objects of the invention, a method for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits is achieved. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas wherein at least one device area is to be silicided and wherein at least one device area is not to be silicided. A composite resist protective oxide layer is formed overlying device areas comprising a first layer of oxide and a second layer of silicon oxynitride. The silicon oxynitride layer is dry etched away overlying the device area to be silicided. Thereafter, the oxide layer is wet etched away overlying the device area to be silicided. Silicidation is performed to complete fabrication of the integrated circuit device.
REFERENCES:
patent: 5863820 (1999-01-01), Huang
patent: 5998252 (1999-12-01), Huang
patent: 6004843 (1999-12-01), Huang
patent: 6010948 (2000-01-01), Yu et al.
patent: 6015730 (2000-01-01), Wang et al.
patent: 6046103 (2000-04-01), Thei et al.
patent: 6200848 (2001-03-01), Lin et al.
Chen Dian-Hau
Chiu Fu-Mei
Wu Lin-June
Ackerman Stephen B.
Nguyen Ha Tran
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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