Row redundancy for flash memories

Static information storage and retrieval – Read/write circuit – Bad bit

Patent

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Details

365203, 365210, G11C 1140

Patent

active

052335593

ABSTRACT:
A method and apparatus for providing row redundancy in non-volatile semiconductor memories is disclosed. This method and apparatus provides for preconditioning of each row of memory cells prior to erasing the memory array, including any rows containing defective cells as well as any redundant rows.

REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4538245 (1985-08-01), Smarandoiu et al.

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