Row redundancy for content addressable memory

Details Row redundancy for content addressable memory Row redundancy for content addressable memory

1999-10-18

2001-08-14

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S049130, C365S230030

Reexamination Certificate

active

06275426

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to performing row redundancy in a content addressable memory (CAM) device.
BACKGROUND
Row and/or column redundancy has been used to improve the yield of memory devices such as static random access memory (SRAM) devices. A fuse element is typically placed in series with each word line in a main memory array. When a memory cell is determined to be defective, the fuse for the corresponding word line is blown to de-couple the main address decoder from the row incorporating the defective memory cell. The address of the defective row is programmed into a spare address decoder that selects a spare row of memory cells in response to subsequent read or write access operations to the defective address in the main memory array.
Traditional row redundancy techniques, however, do not scale well for content addressable memory (CAM) devices. A CAM device is a binary or ternary storage device that can simultaneously compare a specific pattern of comparand data with data stored in each row of CAM cells in its CAM array. Match results are reflected on match lines that are provided to a priority encoder that translates the matched location into a match address or CAM index for output from the CAM device. Each row of CAM cells is typically connected to a word line as in conventional SRAMs and at least one match line. Thus, in order to use traditional row redundancy techniques in a CAM array, each row of CAM cells would use a first fuse for the word line and a second fuse for the match line. Additionally, to ensure that the de-coupled match line did not provide erroneous data to the priority encoder, an additional pull-down circuit would be needed for each match line to guarantee that the de-coupled match line indicated a mismatch state for the defective row of CAM cells. The additional fuse per row, and pull-down circuitry per row, would increase the size of the CAM array. As fuses typically do not scale well with process technologies, this increase in the number of fuses is not readily remedied by migration to a smaller geometry fabrication process.
Thus, it would be desirable to provide a row redundancy scheme for CAMs that is more area efficient than using fuses on each word line and each match line.
SUMMARY OF THE INVENTION
A method and apparatus for performing row redundancy in a CAM device is disclosed. For one embodiment, the CAM device includes a main CAM array having a plurality of rows of CAM cells, main match line control circuitry coupled to the main CAM array, a spare row of CAM cells, and a spare match line control circuit coupled to the spare row of CAM cells. The main CAM array includes a plurality of main match lines each coupled to one of the plurality of rows of CAM cells, and a plurality of main word lines each coupled to one of the plurality of rows of CAM cells. For one embodiment, the main match line control circuitry comprises a plurality of latch circuits each having a data input coupled to one of the main word lines, an output coupled to one of the main match lines, and a clock input responsive to a reset signal and a repair signal. The repair signal indicates whether one of the plurality or rows in the first main CAM array is to be replaced by the spare row of CAM cells. The repair signal is also provided to the spare match line control circuit to enable the spare row of CAM cells when a CAM cell in the main CAM array is determined to be defective. During a reset operation, the latch circuits force a mismatch state on the main match line of a row in the main CAM array that has a defective CAM cell.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.


REFERENCES:
patent: 3633175 (1972-01-01), Harper
patent: 5046046 (1991-09-01), Sweha et al.
patent: 5319589 (1994-06-01), Yamagata et al.
patent: 5644699 (1997-07-01), Yoshida
patent: 5848074 (1998-12-01), Maeno
Tsuneo Mano et al. “A Redundancy Circuit for a Fault-Tolerant 256K MOS RAM,”IEEE Journal of Solid-State Circuits, vol. SC-17, No. 4, Aug. 1982, pp. 726-731.
Robert T. Smith, et al. “Laser Programmable Redundancy and Yield Improvement in a 64K DRAM,”IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981, pp. 506-514.
Yukimasa Uchida, et al. “A Low Power Resistive Load 64 kbit CMOS RAM,”IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, pp. 804-809.

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