Row redundancy circuit using a fuse box independent of banks

Details Row redundancy circuit using a fuse box independent of banks Row redundancy circuit using a fuse box independent of banks

2000-12-21

2002-03-05

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S200000, C365S230030

Reexamination Certificate

active

06353570

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a row redundancy circuit.
PRIOR ART OF THE INVENTION
Generally, because the cost of a semiconductor memory device depends on its yield, redundancy memory cells are added to normal cells to improve the yield. To do this, a method for repairing defective memory cells by replacing them with the redundancy memory cells has been used. However, in highly integrated and large capacity devices higher than 256 Mb, power consumption is increased as a result of unexpected current paths generated during waiting state of the memory device due to bridges generated during processing as the size of a chip is increased. In addition, insufficiency of planer margin due to narrowed line width leads to frequent generation of defects.
FIG. 1
shows a block diagram for the concept of a conventional row redundancy structure. Referring to
FIG. 1
, a memory cell block is divided into 4 banks, with each bank including 8 sub-memory cell blocks. Each of the sub-memory cell blocks includes two redundancy word line pairs, at its top and its bottom, and a redundancy word line driver rwl for selecting and driving a redundancy word line pair. The four banks are aligned in columns to form a fundamental group and the fundamental group includes a fuse box array for selecting the sub-memory cell block and the redundancy word line to be repaired.
In operation, after one of the four banks is selected by a bank selecting circuit, if there is no blown-out fuse in the fuse box of the fuse box array, the output of the fuse box activates a row decoder through a circuit for OR-operating the outputs of the fuses in the fuse box array. If the fuse corresponding to the address of the corresponding sub-memory cell block is blown-out, the output of the fuse box activates the redundancy word line through a circuit for detecting the output signal and deactivates normal word lines.
The fuse box array used with the structure of
FIG. 1
is associated with the banks. That is, when a failed word line is generated in a bank
0
, the fuse in the fuse box associated with the bank
0
should be blown-out indicating needed repair of the failed word line.
In the conventional method for repairing the row word line of the failed bank by using only the fuse box associated with the bank, repair is impossible if the number of the redundancy word lines is larger than that of the word lines having fail bits in a bank.
If the number of the fuse boxes and the redundant word lines are included in the bank in order to solve this problem, repair efficiency is reduced because cost is increased and only the fuse boxes connected within the bank should be used for repairing.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a row redundancy circuit capable of improving repair efficiency by repairing independently of banks.
In accordance with an aspect of the present invention, there is provided a row redundant circuit in a semiconductor memory device, the circuit comprising a fuse box coupled to a row address and a bank address from an address buffer in which a fuse corresponding to an address of a word line to be repaired blows-out; a row fuse decoder for AND-operating two outputs of the fuse box; and a bank row address latching unit coupled to the output of the row fuse decoder for determining the location of a redundant word line in a block to be repaired.


REFERENCES:
patent: 5422850 (1995-06-01), Sukegawa et al.
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5859801 (1999-01-01), Poechmueller
patent: 6141281 (2000-10-01), Mobley et al.
patent: 6185135 (2001-02-01), Netis et al.

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