Row redundancy circuit of a semiconductor memory device

Details Row redundancy circuit of a semiconductor memory device Row redundancy circuit of a semiconductor memory device

1993-07-13

1994-10-11

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

371 102, G11C 700

Patent

active

053553390

ABSTRACT:
Disclosed is a semiconductor device with redundancy for replacing a memory cell with a predetermined defect with additional spare cells. In a semiconductor memory device having a plurality of normal submemory arrays, the present invention discloses a redundancy technique that allows any redundant address decoder to be used with any of the submemory arrays. This maximizes efficiency in redundant repairs as well as maximizes the use of the chip area.

REFERENCES:
patent: 4471472 (1984-09-01), Young
patent: 4885720 (1989-12-01), Miller et al.
patent: 5025418 (1991-06-01), Asoh
patent: 5060197 (1991-10-01), Park et al.
patent: 5124948 (1992-06-01), Takizawa et al.
B. F. Fitzgerald et al., "Memory System with High-Performance Word Redundancy," IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, pp. 1638-1639.

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