Row redundancy block architecture

Details Row redundancy block architecture Row redundancy block architecture

1996-12-03

1997-11-25

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365 63, G11C 506

Patent

active

056919468

ABSTRACT:
Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.

REFERENCES:
patent: 4047163 (1977-09-01), Choate et al.
patent: 4051354 (1977-09-01), Choate
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4586170 (1986-04-01), O'Toole et al.
patent: 4922128 (1990-05-01), Dhong et al.
patent: 5046046 (1991-09-01), Sweha et al.
patent: 5134616 (1992-07-01), Barth, Jr. et al.
patent: 5268866 (1993-12-01), Feng et al.
patent: 5414659 (1995-05-01), Ito
patent: 5422850 (1995-06-01), Sukegawa et al.
patent: 5517442 (1996-05-01), Kirihata et al.
patent: 5625603 (1997-04-01), McClure et al.
W. Cordaro et a,l "Sense Latch Triggering Circuit", IBM Technical Disclosure Bulletin, vol. 26 No. 10B, Mar. 1984.
"Word Line Detector Circuit", IBM Technical Disclosure Bulletin, vol. 29 No. 6, Nov. 1986.
"Fast DRAM Sensing With Sense Amplifiers Synchronous to Bitline Delays", IBM Technical Disclosure Bulletin, vol. 29 No. 10 Mar. 1987.
"Multiplexed Column Redundancy Method for Complementary Metal Oxide Silicon Memory", IBM Disclosure Bulletin, vol. 31 No. 10 Mar. 1989.

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