Row fuse detect circuit

Details Row fuse detect circuit Row fuse detect circuit

1998-04-21

1999-07-13

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36518905, G11C 700

Patent

active

059235985

ABSTRACT:
A row identification circuit identifies which redundant-row fuse has been blown in a memory integrated-circuit by electrically interrogating the integrated-circuit using a switching circuit internal to the memory integrated-circuit. N data output terminals of the memory integrated circuit provide an n-bit binary-coded word which identifies a defective row. To bring out the binary fuse data, the chip is put into a test mode with a TESTF signal which shuts off a normal CMOS transmission gate as well as a latch feedback transmission gate and which turns on another CMOS transmission gate to pass a defective row address bit FUSEB to a data output terminal for the memory device. A switching circuit selectively switches either a defective row address bit TESTB or a data input signal DIN to a data output terminal of the memory integrated circuit. The switching circuit is selectively controlled by a test mode control signal TESTF. For an entire memory integrated circuit, a plurality of switching circuits are provided for each bit of the code word for providing the defective row number.

REFERENCES:
patent: 5555522 (1996-09-01), Anami et al.
patent: 5680354 (1997-10-01), Kawagoe
patent: 5761128 (1998-06-01), Watanabe

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