Static information storage and retrieval – Read/write circuit – Erase
Patent
1992-11-20
1994-03-15
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Erase
36523006, G11C 700
Patent
active
052951065
ABSTRACT:
A row decoding circuit for an EEPROM is described. The row decoding circuit includes a first circuit and a second circuit. The first circuit delivers to a word line a predetermined dc voltage in response to a decode signal during both read operation and write operation and stops delivering the predetermined dc voltage when the word line is selected during erase operation. The predetermined dc voltage is the read voltage when the word line is selected during read operation, is the write voltage when the word line is selected during write operation and is a prescribed voltage level when the word line is not selected during either read operation or write operation. The second circuit delivers to the word line a negative erasure voltage in response to the decode signal when the word line is selected during erase operation and stops delivering any voltage to the word line when the word line is not selected during erase operation. The second circuit stops delivering any voltage to the word line when the word line is selected during both read operation and write operation.
REFERENCES:
patent: 4247918 (1981-01-01), Iwahashi
patent: 4737936 (1988-04-01), Takeuchi
patent: 5039882 (1991-08-01), Arakawa
"An 80-ns 1-Mb Flash-Memory with On-Chip Erase/Erase-Verify Controller", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, pp. 1147-1151, 1990.
"A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16 Mb/64 Mb Flash EEPROMs", Digest of Technical Papers, the 1991 Symposium on VLSI Circuits (IEEE Cat. No. 91, CH 3018.9).
"256K CMOS EPROM", Digest of Technical Papers, The 1984 IEEE International Solid-State Circuit Conference, pp. 183 and 139.
LaRoche Eugene R.
NEC Corporation
Zarahian A.
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