Row decoder for non-volatile memory devices, in particular...

Details Row decoder for non-volatile memory devices, in particular... Row decoder for non-volatile memory devices, in particular...

2011-05-10

2011-05-10

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Amorphous

C365S230030

Reexamination Certificate

active

07940555

ABSTRACT:
A hierarchical row decoder is for a phase-change memory device provided with an array of memory cells organized according to a plurality of array wordlines and array bitlines. The row decoder has a global decoder that addresses first and a second global wordlines according to first address signals; and a local decoder, which is operatively coupled to the global decoder and addresses a respective array wordline according to the value the first and second global wordline and second address signals. The local decoder has a first circuit branch providing, when the first global wordline is addressed, a first current path between the array wordline and a first biasing source during a reading operation; and a second circuit branch providing, when the second global wordline is addressed, a second current path, distinct from the first current path, between the array wordline and a second biasing source during a programming operation.

REFERENCES:
patent: 6233198 (2001-05-01), Choi
patent: 6700822 (2004-03-01), Wang
patent: 6714478 (2004-03-01), Tomita et al.
patent: 7463529 (2008-12-01), Matsubara
patent: 2006/0203550 (2006-09-01), Lee
patent: 2008/0106941 (2008-05-01), Cho

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