Row decoder for NAND-type ROM

Details Row decoder for NAND-type ROM Row decoder for NAND-type ROM

1992-08-31

1994-09-13

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 36523008, 36523005, 365 94, G11C 800

Patent

active

053474937

ABSTRACT:
A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection circuits driven through five buses for implementing a two-level decoding, thus driving less than all of the rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.

REFERENCES:
patent: 4849943 (1989-07-01), Pfennings
patent: 5241511 (1993-08-01), Hsueh
Cuppens, et al., "A 256 Kbit ROM with Serial ROM Cell Structure", IEEE Journal of Solid State Cir., vol. SC-18, #3, Jun. '83 pp. 340-344.
Momodomi, et al., "A 4-Mb NAND EEPROM with Tight Programmed V.sub.t Distribution", IEEE J. SSC., vol. 26, #4, Apr. '1991, pp. 492-496.

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