Row decoder for NAND memories

Details Row decoder for NAND memories Row decoder for NAND memories

2007-02-20

2007-02-20

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185250

Reexamination Certificate

active

11202632

ABSTRACT:
A row decoder for an electrically programmable NAND memory further includes a first means for keeping at least a control node of an addressed memory block charged at a select voltage. A second means decouples all select lines from a global select line. A third means provides an access voltage to the select line corresponding to an addressed memory block for enabling respective access elements and for providing an access inhibition voltage to the select lines corresponding to a non-addressed memory block. The first, second and third means are activatable in a testing operation.

REFERENCES:
patent: 6072719 (2000-06-01), Tanzawa et al.
patent: 6144592 (2000-11-01), Kanda
patent: 6154409 (2000-11-01), Huang et al.
patent: 6249479 (2001-06-01), Tanzawa et al.
patent: 4446998 (1999-06-01), None
European Search Report, EP 04425626, Dec. 10, 2004.

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