Row decoder for a flash-EEPROM memory device with the possibilit

Details Row decoder for a flash-EEPROM memory device with the possibilit Row decoder for a flash-EEPROM memory device with the possibilit

1998-11-25

2000-09-19

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular biasing

36518533, 36518518, G11C 1604

Patent

active

061222003

ABSTRACT:
A row decoder includes a plurality of pre-decoding circuits which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits which, starting from the pre-decoding signals, drive the individual rows of the array of the memory device. Each pre-decoding circuit has a push-pull output circuit with a pull-up transistor and a pull-down transistor and four parallel paths for the signal, a first path, supplied with low voltage, which drives the pull-up transistor during reading; a second path, supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path, supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path, supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages enable selectively one of the first and second path, and one of the third and fourth path, depending on the operative step.

REFERENCES:
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patent: 5513146 (1996-04-01), Atsumi et al.
patent: 5661683 (1997-08-01), Song
patent: 5787037 (1998-07-01), Amanai
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Jinbo, Toshikatsu; Hidetoshi Nakata; Kiyokazu Hashimoto; Takeshi Watanabe; Kazuhisa Ninomiya; Takahiko Urai; Mikio Koiki; Tatsuo Sato; Noriaki Kodama; Ken-ichi Oyama; and Takeshi Okazawa: "A 5-V-only 16-Mb Flash Memory with Sector Erase Mode," 8107 IEEE Journal of Solid-State Circuits 27 (1992) Nov., No. 11, New York, US.

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