Row decoder circuit for non-volatile memory device

Details Row decoder circuit for non-volatile memory device Row decoder circuit for non-volatile memory device

1991-09-03

1993-11-23

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

365185, 36518901, 365218, 36523006, G11C 700

Patent

active

052650626

ABSTRACT:
A row decoder circuit for a non-volatile memory device is disclosed, and the circuit is for erasing, programming and reading the data from the cell comprising of a selecting transistor and a sensing transistor. The required high voltage is supplied to word lines and sense lines from a single high voltage generating section, and when erasing data, a low voltage is supplied to the word line. A transistor for connecting a sense line is connected to each row, in such a manner that the damage liable to occur to the gate oxide layer should be reduced, thereby improving the life expectancy of the chip, and reducing the area of the chip.

REFERENCES:
patent: 4630087 (1986-12-01), Momodomi
patent: 4878203 (1989-10-01), Arakawa
patent: 5022001 (1991-06-01), Kowalski et al.
patent: 5088060 (1992-02-01), Endoh et al.
patent: 5132928 (1992-07-01), Hayashikoshi et al.
"Session X: Nonvolatile Memories"; 1984 IEEE International Solid State Circuits Conference; Sanjay Mehrotra, et al.; pp. 852-858.

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