Row decoder and driver with switched-bias bulk regions

Static information storage and retrieval – Read/write circuit – Using different memory types

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Details

365185, 36518911, 365218, 36523006, G11C 1140

Patent

active

053654790

ABSTRACT:
A novel row decoder/driver circuit in which switched bias voltages are applied to the bulk regions in order to minimize the maximum voltage differential appearing across transistor devices. This allows the decoder/driver circuit to be conveniently fabricated and designed to allow normal transistors rather than more complex and expensive high voltage transistors, to form the row decoder/driver. The bulk regions containing the pull-up and pull-down transistors are biased by voltages which are switched during erasure depending on whether the row line is selected or deselected in order to assure that excessive voltages do not appear across based upon the voltage levels applied to the transistors.

REFERENCES:
patent: 5251172 (1993-10-01), Yamauchi
patent: 5265052 (1993-11-01), D'Arrigo et al.
patent: 5272368 (1993-12-01), Turner et al.
patent: 5287536 (1994-02-01), Schreck et al.
patent: 5291446 (1994-03-01), Van Buskirk et al.
A 5-V-Only 16-Mb Flash Memory With Sector Erase Mode, Jinbo et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992.
A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16Mb/64Mb Flash EEPROMs, Miyawaki et al., LSI R&D Lab., Mitsubishi Electric Corp.
A 5-V-Only Operation 0.6 .mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure, Umezawa et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 11.
NOR Virtual Ground (NVG)--A New Scaling Concept for Very High Density Flash EEPROM and Its Implementation in a . . . , National Semiconductor, IEDM 93-15.
New Erasing and Row Decoding Scheme for Low Supply Voltage . . . Journal of Solid-State Circuits, vol. 27, No. 4, Apr. 1992.

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