Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-03-02
2001-05-22
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S205000, C365S206000, C365S190000, C365S226000
Reexamination Certificate
active
06236606
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to structure and method for row decoded biasing of sense amplifiers for improved one's margin.
BACKGROUND OF THE INVENTION
Modern electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other conventional memory device. The memory device stores data in vast arrays of memory cells. Each cell conventionally stores a single bit of data (a logical “1” or a logical “0”) and can be individually accessed or addressed. Data is output from a memory cell during a “read” operation, and data is stored into a memory cell during a “write” operation.
In a standard read or write operation, a column decoder and a row decoder translate address signals into a single intersection of a row (wordline) and column (digitline, or bitline) within the memory array. This function permits the memory cell at that location to be read from or for data to be placed into that cell. The processing of data is dependent on the time it takes to store or retrieve individual bits of data in the memory cells. Storing and retrieving the bits of data is controlled generally by a microprocessor, whereby data is passed to and from the memory array through a fixed number of input/output (I/O) lines and I/O pins. According to current processing technology the accuracy of sensing data is further dependent on the magnitude of charge stored in a memory cell and the capacitance inherent in the integrated circuit. Typically a logical “1” is stored in a memory cell as Vcc on a storage node side of a capacitor with a potential of Vcc/2 on the common plate of the memory cell capacitor. The capacitor is on the order of 25 femto Farads (fF). When reading the “1” from the capacitor the row line turns on the access transistor between the storage node side of the capacitor and the digit line. The digit line was precharged to Vcc/2 and has a capacitance on the order of 150 to 200 fF. The charge from the storage node dumps onto the digit line and brings its voltage up slightly above the equilibrate level of Vcc/2. Here, +Vcc/2 means a voltage signal slightly greater than Vcc/2, e.g. Vcc/2 plus 50 mV. The reason that the cell only brings the digit up slightly is because of the digit lines large capacitance with respect to the cell. Or to put it another way, the same charge that gets the storage node of the cell to Vcc can only move the digit lines slightly above their equilibrate level of Vcc/2.
When looking at a “0” dumping onto a digitline the same principals apply. Even though the storage node side of the cell is at ground when the row line turns on the access gate to that cell, very little charge from the digitline is needed to get the digitline and cell at the same level. This new level is slightly lower than the digitline's equilibrated level of Vcc/2. In this case, −Vcc/2 will be a voltage signal which is slightly less than Vcc/2, e.g. Vcc/2 minus 50 mV.
A sense amplifier uses the difference between the digitline seeing the cell dump onto it versus the other digitline that remains at the equilibrated level to determine which line to pull up to Vcc and which one to pull down to ground. The accuracy of the sensing operation is thus dependent on the signal clarity between sensing +Vcc/2 and −Vcc/2.
The magnitude of charge required to store a logical “1,” and the rate at which that charge has to be refreshed, contribute to additional operational burdens on the integrated circuit as a whole. Modern applications call on electronic systems to use less power and to process data at greater speeds. In order for electronic systems to meet to these demands, the sensing operation must advance in speed and accuracy.
One method to advance the sensing operation is to bias the sense amplifier in one direction or another, e.g., to favor reading a logical “1” over a logical “0.” Normally, biasing of a sense amplifier is unintentional. When it occurs unintentionally, the sense amplifier affected will tend to fire in the same direction every time, which helps some of the bits on the column and hurts others. Since a logical “1” signal is sometimes weak, the sensing operation may mis-detect an ambiguous logical “1” signal as a logical “0.” To correct for such error, it is desirable to favor sensing a logical “1” over the sensing of a logical “0.” This is done by increasing the signal response range for a logical “1.” Commonly, this is referred to as trading the “zero's margin” for the “one's margin.” One method of favoring logical “1” is by adjusting the digitline equilibrate level. However the equilibration time, which is known as tRP time, is getting too short to allow the digitlines to move from their initial equilibration of Vcc/2.
In example, during equilibration we first short digitline (DIG) and digitline* (DIG*) together. Since one was at Vcc and the other at ground, they both end up at Vcc/2. The digitlines need to be then supplied with a Vcc/2 voltage or they would eventually leak away to ground. This voltage however cannot be supplied directly to the digitlines because any row to column shorts would cause too much current during standby. To combat this effect, Vcc/2 is supplied through a long L n-channel which has high resistance and limits the amount of current that a row to column short can cause. The high resistance also means that it takes a while to get the digitlines to a voltage other than Vcc/2 during the equilibration time. Otherwise stated, it takes a while to get the digitlines to a voltage other than Vcc/2 before the next read in the same memory subarray occurs. This method of trading “zero's margin” for the “one's margin” is being abandoned for this reason. Also, adjusting Vcc/2 to other values causes the margin to vary with cycle time.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop better methods to improve the data sensing operation without an increase in the operational cycle times.
SUMMARY OF THE INVENTION
The above mentioned problems with the sense amplifier operation in memory circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method which accords improved benefits is provided.
In particular, an illustrative embodiment of the present invention includes taking the predecoded the row address signals (i.e. RA123<n>, LPHe<n>, LPHo<n>) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to
Derner Scott J.
Mullarkey Patrick J.
Micro)n Technology, Inc.
Nguyen Viet Q.
Schwegman Lundberg Woessner & Kluth P.A.
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