Row/column address interchange for a fault-tolerant memory syste

Details Row/column address interchange for a fault-tolerant memory syste Row/column address interchange for a fault-tolerant memory syste

1990-05-11

1992-04-28

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523002, 36523003, 371 111, G11C 2900

Patent

active

051093600

ABSTRACT:
A memory system in which access to faulty memory blocks is prevented. A test is carried out to see if there are enough functional memory blocks to store a given amount of information. If not, an address mode signal is generated that interchanges the row/column accesses for a given multi-bit address word, such that a line fault is isolated to only one memory block. This reconfigures the system to maximize available memory space without adding excessive access delays.

REFERENCES:
patent: 4768193 (1988-08-01), Takemae
patent: 5042007 (1991-08-01), Diluna

Affiliated with

Also associated with

Rating

Row/column address interchange for a fault-tolerant memory syste does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Row/column address interchange for a fault-tolerant memory syste, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Row/column address interchange for a fault-tolerant memory syste will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1252849