Row active time control circuit and a semiconductor memory...

Details Row active time control circuit and a semiconductor memory... Row active time control circuit and a semiconductor memory...

2008-01-10

2010-02-02

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

07656741

ABSTRACT:
A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more row active control signals. The row active control signal generating circuit generates a pulse signal that oscillates based on the one or more row active master signals. The row active control signal also generates the one or more row active control signals by dividing a frequency of the generated pulse signal.

REFERENCES:
patent: 7158427 (2007-01-01), Park
patent: 1020040093986 (2004-11-01), None
patent: 1020050067455 (2005-07-01), None
patent: 10-2005-0101683 (2005-10-01), None
patent: 1020050106828 (2005-11-01), None
Office Action for corresponding Korean Application No. 10-2007-0003363 dated Feb. 29, 2008.

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