Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Integrated structure
Reexamination Certificate
2001-01-12
2004-05-25
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Integrated structure
C327S283000, C327S290000
Reexamination Certificate
active
06741122
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to adjusting clock skew.
2. Description of Related Art
Clock skew is a well-known problem, in particular with CMOS switching logic, when there is a difference in propagation delay or phase between two or more signals transmitted along a set of signal lines in parallel, or with a single clock signal transmitted along a long wire where there is transmission delay, e.g., if the clock signal triggers a plurality of rising-edge circuits, one circuit may undesirably react to the clock signal at a different time from another circuit.
To counteract and adjust clock skew, it is known in the prior art to vary the transmission characteristics of a wire trace, such as varying the capacitance and/or resistance of the wire by changing its physical shape, typically by zigzagging the wire so that a transmission signal along the wire has to traverse a longer distance and thus the transmission delay may be varied according to the length of the wire. Thus, as shown in
FIG. 1
(PRIOR ART), a wire trace
10
, having a first endpoint A and a second endpoint B, has a zigzag or corrugated repeating pattern, in an attempt to lengthen the wire trace from the shape of a straight line between A and B. In this manner the propagation delay of a transmission signal may be varied by varying the length of the wire trace between A and B; the longer the wire, the greater the delay. By adjusting the length of the wire an optimal transmission delay may be devised between points A and B.
The problem with the prior art technique of adjusting clock delay as shown in
FIG. 1
(PRIOR ART), compared with the present invention as disclosed herein, is that it is believed there are more resistive losses in the prior art technique of
FIG. 1
(PRIOR ART) than with the present invention, and the surface area covered by the wire of
FIG. 1
(PRIOR ART) is greater than with the present invention, for the same degree of delay. Furthermore, the prior art technique of
FIG. 1
(PRIOR ART) is not as readily adjustable as the present invention; the propagation delay in the
FIG. 1
(PRIOR ART) design is adjusted only by varying the length of the wire between A and B, and, once this length is fixed, the propagation delay is also fixed.
SUMMARY OF THE INVENTION
An aspect of the present invention is to provide a routing design for a wire trace that will achieve the same adjustment to clock skew as in prior art techniques but will have fewer resistive losses and need a smaller area.
Another aspect of the present invention is for a routing design that is relatively easily adjustable to achieve any given propagation delay.
The above described features and many other features and attendant advantages of the present invention will become apparent from a consideration of the following detailed description when considered in conjunction with the accompanying drawings.
REFERENCES:
patent: 5109168 (1992-04-01), Rusu
patent: 5994924 (1999-11-01), Lee et al.
Kapoor Ashok K.
Lin Lei
LSI Logic Corporation
Sawyer Law Group LLP
Wells Kenneth B.
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