Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-21
2002-10-01
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06460169
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to improvements in hierarchical design methods for VLSI chips, and more particularly to a method to identify, in a hierarchically designed chip, those nets with unit pins located in a sub-optimal position.
TRADEMARKS
S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. and Lotus is a registered trademark of its subsidiary Lotus Development Corporation, an independent subsidiary of International Business Machines Corporation, Armonk, N.Y. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
VLSI chips have and continue to grow in complexity due to increasing levels of integration and increasing performance requirements. The time required for a design development cycle for such chips typically increases as the complexity increases. One prior art method used for managing the design complexity and to decrease the design development cycle time is to break down the design into a hierarchical set of components which can be designed concurrently. The physical design methodology to support the hierarchical, concurrent development of components typically employs abstract representations of the lower level (children) components during the design of the higher level (parent) components. This abstraction is required to support concurrent development since the goal is to allow a parent component to be implemented at the same time that its children components are being implemented. The initial abstraction of the children components serves as place holders during the implementation of the parent and contains all required design detail for the parent implementation. One of these details is the positions of terminals (or pins) which serve as connection points to complete physically wired nets which traverse the parent and child hierarchies.
A disadvantage in the hierarchical, concurrent methodology is that the designer of each child (i.e. unit) does not “see” the other children or the parent (top level). Also the top level designer does not “see” the detailed content of each unit but only the abstracted representation. This lack of knowledge of the whole design can lead to sub-optimization or waste. The location of pins at each hierarchical boundary (i.e. unit boundary) may not be optimal, and if not, can increase considerably the length of a net.
SUMMARY OF THE INVENTION
An object of the invention is to provide a method of determining whether or not unit pin placements in the initial design provide minimal net lengths.
Another object of the invention is to identify any sub-optimal initial pin locations so that the pin locations can be optimized, while preserving the benefits of a hierarchical, concurrent physical design implementation. Briefly, this invention contemplates the provision of a method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. Such macro data is not typically used in combination with the top level data, hence the need to create a flat file to bring internal unit data and top level data together with a common nomenclature and a common coordinate description of unit and macro locations. The input for this flat design data file contains unit and macro net names, unit and macro pins assigned to each net, macro and unit physical data including pin shapes, wiring blockage shape data, and unit and macro placement data. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. The data in each pin log lists, for each of the nets in the VLSI chip design, component and instant names, placement locations (including rotation attributes), pin names, and chip (top level translated) x,y coordinates for the shape rectangles that comprise the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. For convenience, the MST or similar program is run against all nets, but only the difference values for nets that leave the units (i.e. have unit pins) are non-zero. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value, that net is identified so that the unit pins can be reassigned by the unit designer or designers. In one embodiment, the designer determines by inspection of the net, in isolation, where to relocate the unit pins. In another embodiment, an MST program is run against each sub-optimum net, in isolation, without unit pins. The point where the “as the crow files line” of the MST program crosses the unit boundaries provides an optimum pin location, although such location may not be precisely physically realizable due to a blockage or crowding of another unit pin. In yet another embodiment, a router program is run in isolation against each net without unit pins. Pins are placed where the wiring route for the net crosses each unit boundary.
REFERENCES:
patent: 5404313 (1995-04-01), Shiohara et al.
patent: 5638293 (1997-06-01), Scepanovic et al.
Camporese Peter J.
Dansky Allan H.
Smith Howard H.
Augspurger Lynn
Cantor & Colburn LLP
Niebling John F.
Whitmore Stacy
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