Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-29
2005-11-29
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06971081
ABSTRACT:
A substrate having a core with vias disposed therein. A reference layer is formed on the core, with voids in the reference layer that are formed around the vias in the core. Traces on a routing layer overlie the reference layer. Also included is a contact layer with contacts disposed in a contact pattern. The core is logically divided into sections, and the vias within a given one of the sections are aligned in rows substantially along a first direction. At least a portion of the vias are not aligned with the contact pattern. The voids in the reference layer within the given one of the sections are also aligned in rows substantially along the first direction and aligned with the vias. Further, the traces within the given one of each of the sections are also aligned substantially along the first direction between the rows of voids, and not substantially overlying the rows of voids.
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LSI Logic Corporation
Luedeka Neely & Graham P.C.
Whitmore Stacy A.
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