Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-10
2002-11-05
Wong, Don (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06477696
ABSTRACT:
FIELD OF THE INVENTION
The present invention relations to a method of layout design of integrated circuit, specifically, to about doing a routing defined modification for standard cells, so as to make the layout optimization.
BACKGROUND OF THE Invention
In the semiconductor manufacturing process, the design of integrated circuit, especially, to application-specific integrated circuit (abbreviated as ASIC), generally, the steps are as follows: firstly, producing a netlist, and then system partitioning and prelayout simulation are successively followed. Next, a floorplanning to arrange the blocks of the netlist on the chip is performed . Thereafter, placing the standard cell in a block. Then perform routing to make connection between cells and blocks. Finally, extracting the resistance and capacitance of the connection, and postlayout simulation to check the design works are carried out. The standard cells includes logic gate, such as NAND, OR, NAND, NOR, AND, XOR and NOT or sequential device, flip-flop, latches, register and so on. After performing simulation for qualified approval, the manufacturing department is then implemented the physical processes in accordance with the layout design.
Generally, to place a standard cell, for example for an inverter, three via pitch distance is demanded. A width of two via pitches is not enough to accommodate such an inverter. A NAND gate with two inputs and one output requires about four via pitches. A NOR gate requires a space almost equivalent to a NAND gate. It is because the pitch width of connection line for standard cells is based on the definition of via-to-via between connection level according to the current design rule.
Please refer to
FIG. 1
, a schematic diagram shows a design of via-to-via about 0.15 &mgr;m feature length process. The metal via width w1 is 0.22 &mgr;m. The surround area to via hole with board width w
2
, w
3
are about 0.05 &mgr;m and 0.01 &mgr;m, respectively. A space s1 between metal board is about 0.24 &mgr;m. And thus a pitch of via-to-via is about 0.56 &mgr;m. However, a width needed for a inverter is about 1.18 &mgr;m according to the design rule. Consequently, if an inverter is placed into a space of two via itches for saving the planar area of wafer. The poly-gate has to form by having about 45° turning angle so as to accommodate the spacing issue. Whereas, for deep sub-micron technology with device feature length of about 0.15 &mgr;m, 0.13 &mgr;m or beyond, the poly-gate with turning angle is not being allowed.
A similar problem is encountered for NAND gate layout. A two-inputs NAND gate, needs a width of about 1.77 &mgr;m. As a consequent, the routing rule according to prior art, of about four via pitches i.e., 2.24 &mgr;m is necessary to fit such a NAND gate. An extra planar area cost cannot be saved.
The layout for standard cells in accordance with the aforementioned prior art is failed to save some extra planar area. However, as is known skilled in the art, the NAND gate, NOR gate, and inverter together are occupied about 70 to 80% of the components for a typical logic circuit using basic standard cells. Thus, the better of the layout design will decide what a degree of the integrity of IC may be, or the chip size while the same amount of devices are placed.
An object of the invention is thus to provide a method which utilize the planar area of a chip fully.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a novel routing definition so as to improve the non-compact layout issues.
The present invention is to provide a routing rule method. The method comprises following steps. At beginning, a statistical analysis is carried out to analyze the standard cells used times in a design plane. The most frequency used types in standard cells is then used as bases for a greatest common divisor (GCD) calculation. The GCD value acquired is then as a routing pitch criterion, which is a distance of contact hole-to-contact hole, or says the standard cell width.
According to the present invention the cross-point between the margins of standard cells along the cell height and the connection lines can be function as substrate contact to increase the cell reliability and
REFERENCES:
patent: 4975854 (1990-12-01), Yabe
patent: 6321371 (2001-11-01), Yount, Jr.
patent: 6324677 (2001-11-01), Fisher et al.
patent: 6327694 (2001-12-01), Kanazawa
patent: 6378121 (2002-04-01), Hiraga
patent: 6385761 (2002-05-01), Bried
A Minh Dieu
Blakely , Sokoloff, Taylor & Zafman LLP
Taiwan Semiconductor Manufacturing Corporation
Wong Don
LandOfFree
Routing definition to optimize layout design of standard cells does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Routing definition to optimize layout design of standard cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Routing definition to optimize layout design of standard cells will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2939302