Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-22
2008-08-26
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07418688
ABSTRACT:
The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step1by a predetermined coefficient α, and a step (Step3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.
REFERENCES:
patent: 7200827 (2007-04-01), Ku et al.
patent: 2002/0133797 (2002-09-01), Sasagawa et al.
patent: 2004/0040007 (2004-02-01), Harn
patent: 10-116915 (1998-05-01), None
Inoue Yoshio
Sadakane Toshiyuki
Saito Ken
Buchanan & Ingersoll & Rooney PC
Dinh Paul
Renesas Technology Corp.
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