Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-31
2006-10-31
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07131095
ABSTRACT:
The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.
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Jia Yongbo
Zhang Shuo
Lumen Intellectual Property Services Inc.
Nannor Technologies
Whitmore Stacy A.
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