ROM with Bi-CMOS gate arrays

Details ROM with Bi-CMOS gate arrays ROM with Bi-CMOS gate arrays

1994-02-24

1995-08-22

Callahan, Timothy P.

Static information storage and retrieval

Systems using particular element

Semiconductive

36518908, 36523003, 36523006, G11C 1134, G11C 800

Patent

active

054446546

ABSTRACT:
Disclosed is a semiconductor integrated circuit of a bipolar CMOS gate array type having a plurality of basic cells arranged in a matrix. Each cell comprises MOS transistors as memory cells, a bipolar transistor, a resistance and bit lines, for transferring data stored in the memory cells to the outside. The semiconductor integrated circuit is characterized in that the basic cells are grouped into a plurality of blocks, the bipolar NPN transistor in each block is used as a driver for reading operations of the data stored in the memory cells in each block, and the bit line is kept at a logic state "0" before the reading operations for the memory cells.

REFERENCES:
patent: 4821235 (1989-04-01), Heald
patent: 4829479 (1989-05-01), Mitsumoto et al.
patent: 4899308 (1990-02-01), Khan
patent: 4933899 (1990-06-01), Gibbs
patent: 5119314 (1992-06-01), Hotta et al.

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