ROM test method and ROM test circuit

Details ROM test method and ROM test circuit ROM test method and ROM test circuit

2005-04-18

2008-07-22

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189030, C365S189120

Reexamination Certificate

active

07403437

ABSTRACT:
The present invention provides a ROM test circuit capable of shortening a test time and a test method therefor. When data written into a plurality of ROMs are tested, data of the ROM(1) and ROM(2) are selected based on the output data of the specific ROM(3). Then, the selected data are compared with expected values to thereby perform testing thereof. Therefore, the contents of the ROM(3) are also tested within the time required to test each of the ROM(1) and ROM(2), thus making it possible to shorten a test time.

REFERENCES:
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patent: 6081908 (2000-06-01), Yamada
patent: 6389564 (2002-05-01), Lu
patent: 6917215 (2005-07-01), Ichikawa
patent: 7136771 (2006-11-01), Terauchi
patent: 2-298877 (1990-12-01), None
patent: 6-052697 (1994-02-01), None
patent: 8-184645 (1996-07-01), None
Official Notice of Reason for Rejection mailed Jul. 25, 2007 in Japanese Patent Application No. 2004-196183 filed Jul. 2, 2004.

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