ROM storing information by using pair of memory cells

Details ROM storing information by using pair of memory cells ROM storing information by using pair of memory cells

2007-12-18

2007-12-18

Lam, David (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S100000, C365S189070, C365S158000

Reexamination Certificate

active

11519232

ABSTRACT:
Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by connecting a MOS transistor and resistor in series are arranged in a matrix. The word lines are connected to the gates of the MOS transistors of the memory cells in the same row of the memory cell array. The bit lines are provided so as to correspond to the columns of the memory cell array. Each bit line is connected to one terminal of a corresponding one of the resistors of the memory cells in the same column. The signal difference determination circuit compares two output signals read to two bit lines from a pair of memory cells, thereby determining stored information in the pair of memory cells.

REFERENCES:
patent: 5313418 (1994-05-01), Wada et al.
patent: 5959877 (1999-09-01), Takahashi
patent: 6741490 (2004-05-01), Baker
patent: 11-026607 (1999-01-01), None
patent: 2003-203994 (2003-07-01), None

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