Robust ultra-low k interconnect structures using...

Details Robust ultra-low k interconnect structures using... Robust ultra-low k interconnect structures using...

2005-08-16

2005-08-16

Chaudhuri, Olik (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000

Reexamination Certificate

active

06930034

ABSTRACT:
A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectric through a perforated bridge layer that connects the top surfaces of the interconnects laterally; performing multilevel extraction of a sacrificial layer; sealing the bridge in a controlled manner; and decreasing the effective dielectric constant of a membrane by perforating it using sub-optical lithography patterning techniques.

REFERENCES:
patent: 6017814 (2000-01-01), Grill et al.
patent: 6261942 (2001-07-01), Zhou et al.
patent: 6265321 (2001-07-01), Chooi et al.
patent: 6346484 (2002-02-01), Cotte et al.
patent: 6413852 (2002-07-01), Grill et al.
patent: 2002/0127844 (2002-09-01), Grill et al.
patent: 2005/0062165 (2005-03-01), Saenger et al.
patent: 2004214648 (2004-07-01), None

Affiliated with

Also associated with

Rating

Robust ultra-low k interconnect structures using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Robust ultra-low k interconnect structures using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Robust ultra-low k interconnect structures using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3483496