Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-13
2003-07-22
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000
Reexamination Certificate
active
06597035
ABSTRACT:
CROSS REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
Pat. No./Ser. No.
Filing Date
TI Case No.
60/109, 729
11/23/98
TI-28390P1
FIELD OF THE INVENTION
The present invention relates to skewed reference circuits for floating-gate memories.
BACKGROUND OF THE INVENTION
Semiconductor memories which do not lose their contents when the power is disconnected are referred to as nonvolatile memories. The most common types of nonvolatile semiconductor memories are those which exploit the properties of a floating-gate transistor. Such a transistor differs from a normal metal oxide semiconductor (MOS) transistor in that a dielectrically isolated floating gate is interposed between a control gate and the channel. (Thus, the two gates are capacitively coupled to each other and to the channel.) The lower gate is called a “floating” gate, because it is electrically isolated from the control gate. By injecting charges into the floating gate, the effective threshold voltage of the MOS transistor (as seen from the upper gate) can be changed. By applying an appropriate voltage to the control gate, and observing whether the transistor turns on, the state of the cell (i.e. whether charge is stored on the floating gate) can be detected. Injecting charges into the floating gate of a MOS memory cell is known as “programming” and the removal of the charge from floating gate is known as “erase”. To read the state of the memory cell a read voltage is applied to the gate and drain of the memory cell. If the transistor has been programmed, then the application of the read voltages to the cell will not result in the formation of a channel because of the high transistor threshold voltage or programmed threshold voltage. Here the memory cell is said to be in the logic “0” state. In the erase state there is no stored charge on the floating gate and the application of the read voltages will result in the formation of a channel. In this case the cell is said to be in the logic “1” state. The two main mechanisms used to program a memory cell are Fowler-Nordheim tunneling or channel hot carrier (CHC) injection. The cells can be erased electrically using Fowler-Norheim tunneling or through the use of ultraviolet (UV) radiation. Semiconductor memory cells which use electrical methods for both programming and erase are known as FLASH EEPROM memory or simply as FLASH memory. All FLASH memory is based on the floating gate concept described above. The FLASH cells can be programmed individually but the content of the entire memory array is always cleared (erased) in one step.
Most FLASH memory uses CHC injection for programming and Fowler-Nordheim tunneling for erase. CHC injection occurs when a relatively large voltage (programming voltage) is placed on the control gate and the drain with the source grounded. The gate and drain voltages produce high electric fields close to the drain causing the channel electrons to gain significant energy in this region of the channel. Some of the channel electrons will gain enough energy to surmount the 3.2 eV gate dielectric barrier and become trapped in the floating gate. For Fowler-Nordheim erase a relatively large erase voltage is placed on the source and the control gate and drain are grounded. The trapped charge on the floating gate will tunnel through the gate dielectric into the source contact.
CHC injection is a well known degradation mechanism in MOS transistors. Repeated CHC injection can result in permanent damage to the gate dielectric of the MOS transistor or FLASH memory cell causing the transistor or cell to become inoperable. For MOS transistors in general, this degradation is caused by broken bonds in the silicon/silicon dioxide interface, generation of interface and bulk traps, and charge trapping, eventually leading to breakdown. In FLASH memory, electron trapping in the tunnel oxide builds up a permanent negative charge, thereby reducing the electric field and the injected electrons. For a constant program voltage or program time, this reduces the programming threshold voltage of the cell, resulting in the threshold window closure problem. Significant window closure typically occurs after about 10
5
cycles (i.e. programming and erase steps) but can be extended using methods such as error correcting codes.
As stated above, in FLASH memory, a logic “1” is defined as the state in which a channel forms at a low threshold voltage (Vt). This occurs in a FLASH memory cell with no excess charge stored on the floating gate. A logic “0” is the state in which the threshold voltage (Vt) of the memory cell is raised (programmed) such that the channel does not form under read voltage conditions. The margin between the threshold voltages of erased FLASH memory cells and of programmed FLASH memory cells must be such that erased cells have threshold voltages below a reference value and programmed cells have threshold voltages above a reference value. This reference value is determined by comparing the selected memory cell to a reference cell in such a way that the reference cell defines a condition, current or voltage, that resides between the logic “1” and logic “0” state of the selected cell. Both the reference cell and the selected cell have the same voltages applied to their control gates during read operations. The comparison to determine whether a logic “1” or a logic “0” is stored on the selected cell is performed by a sense amplifier.
In FLASH memory arrays, a single reference cell can be used to reference many memory cells. For example a single reference cell can be used as the reference for 8, 16, 32, 64 etc. . . memory array columns with each column containing many memory cells. Thus, a reference cell can see 8, 16, 32, 64, etc. . . times more read voltages than the memory array cells. In FLASH memory circuits, the same transistor is typically used for the memory cell and the reference cell. The FLASH memory cell is designed for efficient CHC injection and an identical reference cell will experience some CHC injection during each read operation. Despite the fact that the FLASH memory cell is designed to minimize degradation caused by CHC injection, the reference cell is operated many more times than the memory cell and could have a shorter operating life thus limiting the useful operation lifetime of the FLASH memory circuit. In addition, using the same floating gate transistor for the memory cell and the reference cell imposes unnecessary device deign, process control and circuit design constraints on the reference cell.
SUMMARY OF INVENTION
The instant invention is a method of forming a semiconductor memory with a robust reference sensing cell. The semiconductor memory circuit comprises: an array of memory cells wherein each memory cell comprises a floating gate transistor having a first transistor gate length, a first transistor gate width, and a first drain transition region concentration gradient; and at least one reference cell comprising a floating gate transistor having a second transistor gate length, a second transistor gate width, and a second drain transition region concentration gradient wherein said first drain transition region concentration gradient is greater than said second drain transition region concentration gradient.
Advantages of the instant invention include reduced CHC injection in the reference cell during read operations. Other technical advantages will be readily apparent to one skilled in the art from the following Figures, description, and claims.
REFERENCES:
patent: 5377140 (1994-12-01), Usuki
patent: 5460989 (1995-10-01), Wake
patent: 6052304 (2000-04-01), Chritz
patent: 6281558 (2001-08-01), Sayama et al.
patent: 10-289960 (1998-10-01), None
Brady III W. James
McLarty Peter K.
Nadav Ori
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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