Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2009-02-17
2010-06-08
Chace, Christian P (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S103000
Reexamination Certificate
active
07734891
ABSTRACT:
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.
REFERENCES:
patent: 4876646 (1989-10-01), Gotou et al.
patent: 5247658 (1993-09-01), Barrett et al.
patent: 5287475 (1994-02-01), Sawamoto
patent: 5544356 (1996-08-01), Robinson et al.
patent: 5673383 (1997-09-01), Sukegawa
patent: 5946714 (1999-08-01), Miyauchi
patent: 5978808 (1999-11-01), Wells et al.
patent: 6282605 (2001-08-01), Moore
patent: 6282624 (2001-08-01), Kimura et al.
patent: 6418523 (2002-07-01), Porterfield
patent: 6591329 (2003-07-01), Kakinuma et al.
patent: 6895486 (2005-05-01), Wong et al.
patent: 6928531 (2005-08-01), Wong
patent: 6938140 (2005-08-01), Louie et al.
patent: 2003/0014607 (2003-01-01), Slavin et al.
patent: 2004/0015674 (2004-01-01), Lakhani et al.
patent: 2004/0044836 (2004-03-01), Wong et al.
patent: 2004/0044840 (2004-03-01), Wong
patent: 2004/0044858 (2004-03-01), Wong et al.
patent: 2005/0015378 (2005-01-01), Gammel et al.
patent: 2005/0057973 (2005-03-01), Khatami et al.
patent: 2005/0108491 (2005-05-01), Wong et al.
patent: 2006/0161723 (2006-07-01), Sena et al.
patent: 0 487 331 (1992-05-01), None
Chace Christian P
Farrokh Hashem
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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