Robust delay metric for RC circuits

Details Robust delay metric for RC circuits Robust delay metric for RC circuits

2002-09-26

2004-10-19

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06807659

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to standards of measurement (metrics) for characterizing features of electrical circuits, and more particularly to a method and system which provides a delay metric for resistive-capacitive (RC) networks, such as those in an integrated circuit.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cells types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. An electronic design automation (EDA) system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.), and translates this high level design language description into netlists of various levels of abstraction. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the sub-micron regime, interconnect delays increasingly dominate gate delays. Consequently, physical design optimization tools such as floorplanning, placement, and routing are becoming more “timing-driven” than the previous generation of tools. For such a tool to be effective, it must be able to efficiently compute interconnect delay since several million delay calculations are required to optimize a design.
In certain types of circuits, delays exist based on circuit topology and circuit components. Delays are particularly acute in circuits having resistive and capacitive elements, or RC circuits, as they are called in the art. A schematic diagram showing a generalized RC circuit is shown in FIG.
1
. Circuit designers continually search for efficient techniques for accurate estimation of these delays, while determining the particular circuit's response to a load. In particular, circuit designers want to be able to calculate reliable delay information when designing the circuit. To this end, several prior art metrics (i.e., computational methods) have been developed.
The Elmore delay metric, which calculates the first moment of the impulse response, is the most widely applied and simplest interconnect delay metric that still captures some amount of metal resistance effects. The Elmore metric provides an upper bound on delay given any input waveform because the RC circuit impulse response is unimodal and positively skewed. The Elmore delay metric is commonly utilized for performance optimization tasks such as floorplanning, placement, buffer insertion, wire sizing in part and global routing. The widespread use of the Elmore delay metric is due to its closed form expression, fast computation speed, and fidelity with respect to simulation. Closed form delay equations, such as Elmore delay metric, are certainly preferable due to both efficiency and ease of implementation, as long as they are sufficiently accurate.
Despite its wide usage, the Elmore delay metric is known to be extremely inaccurate at times because it ignores the resistive shielding of downstream capacitance. For example, in the simple RC network as shown in
FIG. 1
, the Elmore delay to capacitor C
1
at node N
1
, is independent of the resistors (R
2
to R
10
). The higher the value of these resistors, the more the downstream capacitance is shielded, i.e., the larger the error is for the Elmore approximation. Particular values may be chosen for the various circuit elements in
FIG. 1
, which can result in arbitrarily large errors when analyzed with the Elmore delay metric. Errors of up to several hundred percent have been recorded when the Elmore delay metric is utilized for sub-micron technologies. Errors from Elmore delay metric are generally much more pronounced for near-end nodes (nodes relatively close to the power source) than for far-end nodes (nodes relatively far from the power source) since resistive shielding is not as much of a factor for far-end nodes.
To achieve greater accuracy than the Elmore delay metric can provide requires additional moments of the impulse response. However, moment matching does not directly produce a delay approximation, but rather a reduced order response, which can be solved via nonlinear iterations. These iterations tend to dominate the runtime of the entire delay computation method. Thus, several prior art methods have sought to circumvent iterations by proposing delay approximations metrics that are direct functions of the circuit moments.
Several of the other traditional metrics are known to be more accurate but are either CPU intensive or difficult to implement. For example, moment matching via asymptotic waveform evaluation (AWE) is very accurate but too computationally expensive to use within a tight optimization loop. Two-pole variants of AWE are considerably faster and recognized to be more accurate than the Elmore delay metric, but are still relatively expensive, as nonlinear solution methods such as Newton-Raphson iterations need to be run to solve the transcendental equation. The computational cost of this approach is expensive and can have a negative impact on the overall speed of the physical optimization. Also, their solutions may be unstable, i.e., poles may be positive; hence special care has to be taken to ensure stability. First order delay estimates, which are derived from the dominant pole and corresponding residue, also requires subsequent Newton-Raphson iterations. The metric commonly referred to as PRIMO fits the moments of the impulse response to probability density functions by utilizing a table lookup operation. The h-gamma metric (which subsumes PRIMO) avoids time-shifting the distribution functions and matches the moments to the circuit's homogenous response. The gamma solution also requires a lookup table which is not trivial to build. The scaled Elmore delay metric shifts the Elmore approximation and the error, but does not change the relative delay error problem.
Another closed form RC delay metric is described in U.S. Pat. No. 6,434,729, which calculates two moments of impulse response for an RC circuit, and computes a delay value for each node of the circuit based on these two moments. Each node is analyzed to determine if the delay at the given node is at a desired optimization condition. While this metric is useful for calculating the 50% delay, it

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