Robust 8T SRAM cell

Details Robust 8T SRAM cell Robust 8T SRAM cell

2008-09-26

2010-10-05

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S158000

Reexamination Certificate

active

07808812

ABSTRACT:
This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.

REFERENCES:
patent: 6542401 (2003-04-01), Yamauchi et al.
patent: 6590802 (2003-07-01), Nii
patent: 6606276 (2003-08-01), Yamauchi et al.
patent: 7177177 (2007-02-01), Chuang et al.
Ramadurai, Vinod et al., “A Disturb Decoupled Column Select 8T SRAM Cell”, IEEE 2007 Custom Intergrated Circuits Conference (CICC), pp. 25-28.

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