RISC processor architecture with high performance context switch

Details RISC processor architecture with high performance context switch RISC processor architecture with high performance context switch

1998-04-22

2000-10-17

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Processing control

Context preserving (e.g., context swapping, checkpointing,...

709109, 712 41, G06F 948

Patent

active

061346535

ABSTRACT:
A RISC processor includes a sequencer, a register ALU (RALU), data RAM, and a coprocessor interface. The sequencer includes an N.times.32 bit instruction RAM which is booted from external memory through the coprocessor interface. The RALU includes a four port register file for storage of three contexts, and an ALU. The ISA (instruction set architecture) according to the invention supports up to eight coprocessors. An important feature of the invention is that multiple sets of general purpose registers are provided for the storing of several contexts. According to a presently preferred embodiment, three sets of general purpose registers are provided as part of the RALU and a new opcode is provided for switching among the sets of general purpose registers. With multiple sets of general purpose registers, context switching can be completed in three processing cycles. In addition, one set of general purpose registers can be loaded by a coprocessor while another set of general purpose registers is in use by the ALU. According to a presently preferred embodiment, each of the three sets of general purpose registers includes twenty-eight thirty-two bit registers. In addition, according to the presently preferred embodiment, a single set of four thirty-two bit registers is provided for use in any context. The set of common registers is used to store information which is used by more than one context.

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