Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1993-02-05
1996-05-21
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257295, 257296, 257308, H01L 2968, H01L 2978, H01L 2992
Patent
active
055192386
ABSTRACT:
A new method to produce a microminiturized capacitor having a regular microscopic ripple surface electrode is achieved by depositing a first polysilicon layer over a suitable insulating base. A resist layer is formed over the first polysilicon layer. The resist layer is exposed through a mask having a pattern of regular spaced openings in the areas of the planned capacitor to radiant energy in sufficient quantity to under expose, out of focus expose or a combination of under expose and out of focus expose the resist layer. The mask is shifted a fixed and short distance. The resist layer is exposed through the shifted mask to radiant energy in sufficient quantity to under expose or out of focus expose, or a combination of under expose or out of focus expose the resist layer again and in a different location. The shifting of the mask and exposing resist steps are repeated until a pattern of the regular microscopic ripple has been formed in the resist layer. The resist layer is developed to leave the pattern of regular microscopic ripple in the surface of the resist layer. The resist layer and said first polysilicon layer is uniformly and anisotropically etched to create the pattern of regular microscopic ripple in the surface of the first polysilicon layer. The remaining resist layer is removed. An insulating layer is deposited over the ripple surface. The capacitor structure is completed by depositing a second polysilicon layer over the insulating layer.
REFERENCES:
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5082797 (1992-07-01), Chan et al.
patent: 5130885 (1992-07-01), Fazan et al.
Sakao et al., "A Capacitor-Over-Bit-Line (COB) Cell With a Hemispherical-Grain Storage Node for 64 Mb DRAMs", IEDM Technical Digest, 1990, pp. 655-658.
Yoshimaru et al., "Rugged Surface Poly-SC Electrode and Low Temperature Deposited Si.sub.3 N.sub.4 For 64MBIT And Beyond STC DRAM Cell", IEDM Technical Digest, 1990, pp. 659-662.
Fazan et al., "Electrical Characterization of Textured Interpoly Capacitors for Advanced Stacked DRAMs", IEDM Technical Digest, 1990, pp.663-666.
"Increased Surface Area Capacitor by Laser Intereference", IBM Technical Disclosure Bulletin, vol. 34, No. 4A, Sep. 1991, pp. 433-434.
Crane Sara W.
Industrial Technology Research Institute
Saile George O.
Tang Alice W.
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