Ring interconnect with multiple coherence networks

Details Ring interconnect with multiple coherence networks Ring interconnect with multiple coherence networks

2008-07-29

2008-07-29

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S003000, C711S141000, C711S143000, C711S146000, C711S167000, C710S011000, C710S036000, C710S038000, C710S100000, C709S213000, C709S216000, C709S218000, C709S238000, C709S251000, C709S245000

Reexamination Certificate

active

07406566

ABSTRACT:
A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each communication with the same protocol agent, which may or may not be integrated within any one of the cache agents. Embodiments of the invention also include protocol agents capable of storing multiple sets of data from different sets of cache agents within the same clock cycle.

REFERENCES:
patent: 6253292 (2001-06-01), Jhang et al.
patent: 6611906 (2003-08-01), McAllister et al.
patent: 6988173 (2006-01-01), Blake et al.
patent: 2004/0008721 (2004-01-01), Ying et al.

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