Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1999-08-04
2001-05-08
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
83
Reexamination Certificate
active
06226863
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, more particularly, to an apparatus and method for enabling the reworkability of an integrated circuit
BACKGROUND OF THE INVENTION
Circuit boards with multiple Very Large Scale Integrated (VLSI) circuit chips are called Multi-Chip Modules (MCM) The use of VLSI circuits presents interface problems relating to the interconnection of the integrated circuits to other circuits and the placement of the integrated circuits on a ceramic circuit board (MCM-C) As VLSI technology has advanced, the density of circuits on a single VLSI chip has increased and the necessary interconnection for VLSI chips has become increasingly difficult to achieve in a limited space.
In a typical configuration, semiconductor chips are mounted in cavities on multilayer circuit boards or substrates and the substrates accommodate intercircuit connections through tiny vertical holes or vias between the layers. In the case of wirebond chips, the chips are connected to the vias using bonding wires which are welded to the interconnection pads on the chip and the pads connected to the vias on the substrate. The vias are filled with a conductive material, such as molybdenum paste, which creates a connection to the VLSI circuit.
Reworkability is an issue for a wirebond chip which is attached to a substrate. This is generally not an issue for Single Chip Modules (SCMs), where the chip carrier can be thrown away (with the chip) after burn-in and test. For MCMs where only wirebond chips are used, however, reworkability is mandatory to prevent loss of the entire module, even if bare die burn-in has preceded chip attachment.
FIG. 1
shows a typical application using a wirebond chip. In
FIG. 1
, wirebond chip
10
is mechanically attached to substrate
12
by bonding agent
14
. Wirebond chip
10
is electrically connected to substrate
12
by bonding wire
16
at via
18
. This prior art application has the disadvantage that removal of wirebond chip
10
from substrate
12
results in loss of the module due to the nature of the removal process, as well as the destruction of the wirebond chip, preventing defect analysis and diagnostics of the chip.
Reworks in high speed MCMs are driven primarily due to speed imbalances among the individual chips on the MCM. This problem is exacerbated with Complementary Metal Oxide Semiconductor (CMOS) technology, where speed sorts of wafer level burn-in carriers are accurate to only within 10-15%. So an MCM designed to run at 100 MHz may not function properly with a microprocessor chip sorted at 90±10 MHz. This has been borne out by recent experiences with MCMs.
In addition to the reworkability issue, high performance micros/Application Specific Integrated Circuit (ASIC) chips require a large amount of decoupling. capacitance (1 to 3 &mgr;F). Because a wirebond chip image is significantly larger than an equivalent controlled-collapsed-chip-connection (C4) chip image on an MCM, on module discrete decoupling capacitors do not work as well as capacitors that lie directly beneath the chip. U.S. Pat. No. 5,095,402 issued to Hernandez et al. illustrates a decoupling capacitor placed within an integrated circuit package. As illustrated in
FIG. 2
, wirebond chip
20
is attached to an IC carrier
22
. Bonding wire
26
electrically connects wirebond chip
20
with pads
28
of carrier
22
. A decoupling capacitor
24
is attached to wirebond chip
20
. This prior art also exhibits the drawback that wirebond chip
20
cannot be removed from carrier
22
without destroying the carrier.
FIG. 3
shows a typical MCM which has nine sites
32
for mounting dice
34
,
36
, etc. If, for example, die
34
is defective due to an improper wirebond, solder joint, or speed intolerance, the entire MCM
30
must be scrapped because conventional mounting methods of dice
34
,
36
, etc. do not provide for non-destructive removal of the defective die
FIG. 4
illustrates a conventional method of mounting electronic components
40
to a substrate
42
. This conventional method uses solder balls
44
to attach component
40
to substrate
42
. This method has a drawback, however, in that decoupling capacitors (not shown) must be attached to substrate
42
at locations remote from component
40
. In addition, physical constraints limit the amount of decoupling available to any given component. This results in insufficient decoupling of high frequency noise resulting in inferior high speed performance of the assembled MCM.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an apparatus and method for enabling the reworkability of an integrated circuit. It is another object of the present invention to enhance the operation of an integrated circuit. It is a further object of the present invention to provide a carrier substrate to attach to a wirebond chip which allows for reworkability of an integrated circuit attached to a multi-chip module. It is another object of the present invention to provide a reworkable multi-chip module with a decoupling capacitor integral with each wirebond chip. Still another object of the present invention is to provide a wirebond chip attached to a substrate which is attached to a multi-chip module using ball grid array (BGA) or controlled collapse chip connection (C4) attachment methods. It is another object of the present invention to provide a burn-in test vehicle capable of operating at speeds of up to 800 MHz. Finally, it is another object of the present invention to allow non-destructive diagnostics of a chip wire bonded to a carrier.
SUMMARY OF THE INVENTION
An interposer is manufactured incorporating an integral capacitance layer. The top surface of the interposer has wirebond pads to accept a wirebond chip. The wirebond chip is die attached and then bonded to the pads on the top surface metallurgy (TSM). The wirebond pads on the TSM pads are connected to the bottom surface metallurgy (BSM) by thru vias. The BSM is C4 pads or BGA pads. Using this structure, a wirebond chip from a package can now be removed and replaced without the loss of the entire package. Previously, it was not possible to rework a wirebond chip, and thus wirebond chips were never placed on MCM's as one defective or out-of-tolerance chip caused the entire module to be scrapped.
Using the integral capacitance layer interposer, when a wirebond chip fails, the interposer can be removed by either hot vacuum or in-situ device removal. In hot vacuum, the module is placed in a box oven and at liquidous temperature and the interposer is lifted from the module by means of vacuum. In in-situ device removal, the interposer is gripped and lifted from the module at liquidous temperature through a belt furnace using bimetallic disks to cause the lifting action. The module site is then dressed of residual solder by either copper block or shave process and a replacement interposer is reattached to the module.
To solve the aforementioned disadvantages of conventional integrated circuit mounting arrangements, the present invention relates to an apparatus and method for enabling the reworkability of an integrated circuit. The apparatus comprises a wirebond chip and a carrier substrate. The wirebond chip is attached to the top of the carrier substrate and is electrically connected to the bottom surface of the carrier substrate. The dielectric layer provides high decoupling capacitance which is required to minimize power supply noise in high speed processors.
The present invention also relates to an apparatus for enabling the reworkability and operation of an integrated circuit employing a wirebond chip, a carrier substrate, and a dielectric layer attached to the surface of the carrier substrate.
The present invention further relates to an apparatus for mounting a wirebond chip to a module using a carrier substrate having structure for connecting the carrier substrate to the wirebond chip, a dielectric layer attached to the carrier substrate, and a device f
Farooq Mukta Shaji
Jackson Raymond Alan
Ray Sudipta Kumar
Arbes Carl J.
International Business Machines - Corporation
Ratner & Prestia
Townsend, Esq. Tiffany L.
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