Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-05
2002-03-05
Fabmy, Jr., Wael (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S685000, C438S644000, C438S648000, C438S672000, C252S079100
Reexamination Certificate
active
06352924
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and, more particularly, to a method to rework tungsten plugs on the surface of a wafer by providing a new TiN glue-layer in the opening for the tungsten plug after which a layer of tungsten is re-deposited.
(2) Description of the Prior Art
In the formation of integrated circuits in a semiconductor substrate, the silicon wafer is populated with active devices. These active devices are isolated from adjacent active devices by well known techniques in the art such as the formation of Shallow Trench Isolation (STI) areas, of which the Burried Oxide (BOX) process is one example, and the creation of Field Oxide (FOX) isolation regions. The BOX process uses shallow trenches that are filled with a chemical vapor deposition (CVD) of silicon oxide (SiO
2
) and then etched back or mechanically or chemically polished to yield a planar surface. The shallow trenches etched for the BOX process are anisotropically plasma etched into the silicon substrate and are typically between 0.5 and 0.8 micrometer (um.) deep. STI's are formed around active devices to a depth between 4000 and 20000 Angstrom.
The active devices that are formed in a semiconductor substrate are interconnected with specific electrical paths where thin-film paths of high-conductivity material are applied as the interconnection medium. An isolating layer shields the active devices from the environment; openings are created through the isolating layer through which the electrical contacts are established between the active devices and the network of interconnecting conducting wires. The electrical contacts that are in this manner established must be low resistivity contacts and must have good characteristics of planarity, connectivity and reliability. For devices in the micron and sub-micron scale, the requirement of fabricating good contact holes and vias imposes increasing demands of process complexity and control.
It is clear that it is important to overall device performance to create low-resistance ohmic contacts at the device level. One technique used to achieve this objective is the application of dopants in the area of the substrate where electrical contact has to be established. By increasing the dopant concentration in these contact areas, the contact resistance decreases, this up to the point where the dopant solubility has been reached for the area that is being doped for the temperature at which the dopant is introduced. A further factor that has an impact on plug contact resistance is the cleanliness of the substrate surface at the time that the contact plug is being formed. Unclean substrate surfaces will result in increased contact resistance and must therefore be avoided. A further concern is the formation of a layer of native oxide on the surface of the substrate due to the rapid oxidation of silicon when silicon is exposed to an oxygen ambient.
Current technology makes frequent use of contact plugs that use tungsten or, more recently, copper as filler for the contact openings.
For the formation of tungsten (W) contact holes, the process typically starts with the deposition of an insulating layer, openings are patterned into this layer in the areas where electrical contacts must be established with the active devices. Next a glue layer, typically of titanium, is deposited on the sidewalls and bottom of the created openings over which a barrier layer, typically of titanium nitride, is deposited. The barrier layer serves the purpose of preventing gasses, such as WF
6
, that are created during the tungsten deposition, from penetrating into the tungsten that is being deposited and, in doing so, cause surface dislocations on the deposited tungsten. The deposition of the barrier layer of TiN can be enhanced by applying a Rapid Thermal Anneal (RTA) immediately after the barrier layer has been deposited and before the tungsten is deposited. The RTA improves the surface conformity of the deposited barrier layer. The barrier layer can be deposited by reactive sputtering or by Chemical Vapor Deposition (CVD). With increasingly smaller device dimensions, the CVD techniques offer the advantage of providing good conformity independent of the thickness of the deposited layer of TiN. The deposited layer of tungsten is etched back. The process of metalization can then be completed by depositing a layer of a conducting material, for instance aluminum, and patterning this layer into the desired interconnecting pattern. Care must be taken that during the etchback for the metalization pattern the previously deposited barrier layer is not removed from the top areas of the created contact holes thereby exposing the titanium underlayer. This would result in oxidation of the titanium underlayer, which would prevent the etching of the titanium layer resulting in residues that can cause electrical shorts in the metal interconnect.
Frequently used metal layers to form the metal interconnects are metal layers that react with the underlying silicon to form suicides. For this purpose titanium silicide can be used in view of the excellent operational characteristics of titanium silicide (TiSi
2
) in a semiconductor environment. TiSi
2
has, for instance, excellent oxygen getter abilities while it forms good ohmic contact with both polysilicon and doped areas in single-crystal silicon. Silicides offer the advantage of reducing native oxide on the surface of the substrate after annealing processes. The titanium in the formed silicides reacts with native oxide and forms titanium oxide and titanium silicide, these materials are excellent conductors and remain on the surface of the formed silicide layer after the process of annealing has been completed.
As highlighted above, assuring adequate metal contact and metal continuity in contact windows and vias is important in establishing low resistivity contacts between metal layers and other device components. Where metal contacts are in the micron or sub-micron regions, metal penetration into the contact opening is often difficult to achieve and, as a consequence, step coverage at contacts of sputtered metal will be dramatically reduced. This has led to the formation of a number of different types of contact plugs; these contact plugs in essence use aluminum or tungsten as contact fill material.
Aluminum plugs have recently been investigated where the aluminum plug is formed at high temperatures. After deposition of the aluminum plug, the plug can be re-flowed by a high temperature anneal or by excimer laser to establish good plug planarity. Of these two approaches, the reflow process is the less desirable since this process causes plug junction damage due to the long time delay incurred before the solidification of aluminum, during this process of solidification the aluminum reacts with the barrier material. The excimer laser approach requires considerable laser power output since aluminum is a highly reflective material in the UV range; damage to the barrier layer is however avoided with this process. Using anti-reflective coatings can reduce the required laser output. The application of lasers for the formation of aluminum plugs however results in the formation of metal alloys with the aluminum, these alloys all have high resistivity and are therefore undesirable in a semiconductor device. For this reason this latter approach has so far not found wide application.
The formation of aluminum plugs has further been investigated by in situ reflow of cold aluminum. This leads to problems of aluminum wetting between the aluminum and the aluminum barriers, which in turn leads to the use of composite wetting barriers such as Ti/TiN and others. Overall, sub-micron contact openings make it difficult to use aluminum-based metalization as a contact hole fill material. It is difficult to deposit aluminum using CVD techniques while sputtered aluminum does not produce the desired material deposition that is needed to adequately fill sub-micron holes with aluminum. The not-uniform m
Lee Ming Jer
Lin Yu Ku
Wang Ying-Lang
Wu Jun
Ackerman Stephen B.
Fabmy Jr. Wael
Saile George O.
Taiwan Semiconductor Manufacturing Company
Toledo Fernando
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