Reversed damascene process for multiple level metal...

Details Reversed damascene process for multiple level metal... Reversed damascene process for multiple level metal...

2000-06-21

2002-03-05

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000, C438S638000, C438S639000

Reexamination Certificate

active

06352917

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming reversed damascene metal interconnects in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Damascene technology is an important capability in the present art of semiconductor manufacturing. Damascene and dual damascene schemes facilitates the use of copper for interconnects. Copper offers significant advantages due to its low resistivity when compared to aluminum.
Referring now to
FIG. 1
, a prior art dual damascene structure is illustrated. In this cross-sectional representation, three interconnect levels are shown. A substrate
10
contains via plugs
18
that connect, for example, to an underlying transistor junction (not shown).
The formation of the single damascene first level interconnect layer is as follows. The intermetal dielectric (IMD) layer is formed first. The first IMD etch stop layer
14
overlies the substrate
10
. The first IMD dielectric layer
22
is deposited overlying the first etch stop layer
14
and the via plugs
18
. The first IMD dielectric layer
22
is then etched to form trenches. A first level conductive barrier layer
28
is deposited to line the trenches. A first level copper layer
26
is deposited to fill the trenches. The first level copper layer
26
and the first level conductive barrier layer
28
are then polished down. Finally, a first level capping or passivation layer
30
is deposited overlying the first level copper layer
26
to complete the first level interconnect layer. This first level is created in a typical single damascene approach where a single level trench is etched and filled with metal to form a single interconnecting structure (the interconnect trace).
The second and third metalization layers are formed using a typical dual damascene approach. In a dual damascene approach, a two-level trench is etched and then filled with a single metal layer to form two interconnecting structures (both the interconnect line and the via). The second intermetal dielectric (IMD) is formed first. In this example, the second IMD comprises a dielectric stack consisting of the second IMD lower dielectric layer
34
, the second IMD etch stop layer
38
, and the second IMD upper dielectric layer
42
. The trenches are etched in two steps. The second IMD etch stop layer
38
facilitates etching two-level trenches. The lower level of the trenches will form the vias to connect the second interconnect level to the first interconnect level. The upper level of the trenches will form the second level interconnect lines. After trench formation, the second level conductive barrier layer
48
and the second level copper layer
46
,
50
,
54
are deposited. A polish down is used to define the interconnections. A second level capping or passivation layer
58
is deposited to finish the second level. Note the two levels of the dual damascene structure. The lower level
50
is the via. The upper level
54
is the interconnect line. The third interconnect level is formed using the same method as used for the second level.
Several problems exist in the prior art dual damascene interconnect method. First, it is difficult to deposit the conductive barrier layer. For example, the third level conductive barrier layer
76
must be deposited in the dual damascene trench for the third level. A seed layer of copper is deposited after the barrier layer to catalyze the copper deposition. Insufficient barrier layer step coverage along the sidewall
101
and at the bottom
105
can occur due to the high aspect ratio of the trench in the via level. The insufficient coverage, that may result in voids, can cause copper deposition and diffusion problems. The second problem in the prior art is copper layer voids. For example, voids may occur during the deposition of the third level copper layer
86
,
82
. Again, the very high aspect ratio of the via level of the trench can cause this problem.
The third problem is that the two-level trenches require the use of many etch stop layers
103
. For example, the third level etch stop layer
66
is used to facilitate the definition of upper and lower trench levels for the third level trenches. In addition, the third level capping or passivation layer
74
is likewise an etch stop layer. These etch stop layers
103
typically comprise silicon nitride that has a relatively high dielectric constant. The use of these etch stop layers
103
adds significantly to the parasitic capacitance of each interconnect level and reduces circuit performance. Finally, the fourth problem is that the via can misalign
104
to the underlying metal interconnect. Such misalignments increase the via resistance and degrade circuit performance.
Several prior art approaches disclose methods to form interconnecting layers. U.S. Pat. No. 5,693,568 to Liu et al discloses a process to form interconnect layers in an integrated circuit device. Interconnect lines and vias are formed for each interconnect level. A composite metal layer is deposited comprising three layers: an upper metal layer, an etch stop layer, and a lower metal layer. The composite metal layer is first etched through. A first dielectric layer is then deposited to fill the spaces between the etched composite metal. The upper metal layer is etched down to the etch stop layer to pattern the vias. A second dielectric layer is then deposited to fill gaps caused by the second etching. This method reverses the order of the vias and interconnects compared to the prior art though it is not a damascene process since the metal is patterned only by etching. U.S. Pat. No. 5,512,514 to Lee teaches a process to form interconnect levels. No barrier metal is used underlying the metal layer. The metal layer is etched twice. The first etch is partially through the copper and defines via plugs. The second etch is completely through the metal layer and defines the interconnect pattern. No non-conductive barrier layer is applied overlying the patterned metal layer. After both etch steps, a dielectric layer is deposited to isolate the level. This process also reverses the typical order of the via and the interconnect. This process is likewise not a damascene process since both via and interconnect lines are formed by etching and not by trench filling. U.S. Pat. No. 5,926,732 to Matsuura discloses a dual damascene process. In this method, the vias are formed below the interconnects as in the prior art example. An etch stop layer is used to stop the via level trench etch from penetrating to the previous level dielectric layer. U.S. Pat. No. 5,691,238 to Avanzino et al discloses a subtractive dual damascene approach. The via mask extends perpendicularly across the width of the interconnect pattern to allow a self-aligned etch. Aluminum is used for the metalization. U.S. Pat. No. 5,882,996 to Dai discloses a self-aligned dual damascene process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method to form metal interconnect levels in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to form metal interconnect levels by using a reversed damascene process whereby via plugs are formed overlying and from the same metal layer as the conductive lines.
A still further object of the present invention is to form metal interconnect levels whereby the conductive lines are produced by etching trenches into a dielectric layer and then depositing metal to fill the trenches.
Another still further object of the present invention is to form via plugs by partially etching the metal layer.
Another still further object of the present invention is to simplify barrier layer lining deposition.
Another still further object of the present invention is to provide a method to simplify metal layer deposition.
Another still further object of the present invention is to eliminate one etch stop layer for each level.
Anoth

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